diff options
| author | Sowjanya Komatineni <skomatineni@nvidia.com> | 2019-04-15 14:30:26 -0700 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2019-05-02 10:38:40 +0900 |
| commit | cc1b69fc5f9f52cf18295db05cad57187cee1c1d (patch) | |
| tree | f982b431aea0c1eb7da7e2faa5262ebff0e51d7e /drivers/spi/spi-tegra114.c | |
| parent | 29f2133717c527f492933b0622a4aafe0b3cbe9e (diff) | |
spi: tegra114: fix PIO transfer
This patch fixes PIO mode transfer to use PIO bit in SPI_COMMAND1 register.
Current driver uses DMA_EN instead of PIO bit.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi/spi-tegra114.c')
| -rw-r--r-- | drivers/spi/spi-tegra114.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index b57f10182fae..21e4fdad013f 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c @@ -641,8 +641,9 @@ static int tegra_spi_start_cpu_based_transfer( tspi->is_curr_dma_xfer = false; - val |= SPI_DMA_EN; - tegra_spi_writel(tspi, val, SPI_DMA_CTL); + val = tspi->command1_reg; + val |= SPI_PIO; + tegra_spi_writel(tspi, val, SPI_COMMAND1); return 0; } |