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authorThierry Reding <thierry.reding@gmail.com>2020-06-15 16:08:28 +0200
committerThierry Reding <thierry.reding@gmail.com>2020-06-17 20:42:09 +0200
commit5bc5d99f1f836858820ad8e9a412bb103bb0d88b (patch)
treeb438d6b38415f035a6b2ae3bc5e3296104dd77f8 /drivers/pwm/pwm-iqs620a.c
parent1689dcd433aaa0d32dec3fdb4bd166a0d38f4bbf (diff)
pwm: iqs620a: Use 64-bit division
The PWM framework is going to change the PWM period and duty cycles to be 64-bit unsigned integers. To avoid build errors on platforms that do not natively support 64-bit division, use explicity 64-bit division. Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Diffstat (limited to 'drivers/pwm/pwm-iqs620a.c')
-rw-r--r--drivers/pwm/pwm-iqs620a.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/pwm/pwm-iqs620a.c b/drivers/pwm/pwm-iqs620a.c
index 674f0e238ba0..b2bb27eff623 100644
--- a/drivers/pwm/pwm-iqs620a.c
+++ b/drivers/pwm/pwm-iqs620a.c
@@ -46,7 +46,8 @@ static int iqs620_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
{
struct iqs620_pwm_private *iqs620_pwm;
struct iqs62x_core *iqs62x;
- int duty_scale, ret;
+ u64 duty_scale;
+ int ret;
if (state->polarity != PWM_POLARITY_NORMAL)
return -ENOTSUPP;
@@ -69,7 +70,7 @@ static int iqs620_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
* For lower duty cycles (e.g. 0), the PWM output is simply disabled to
* allow an external pull-down resistor to hold the GPIO3/LTX pin low.
*/
- duty_scale = state->duty_cycle * 256 / IQS620_PWM_PERIOD_NS;
+ duty_scale = div_u64(state->duty_cycle * 256, IQS620_PWM_PERIOD_NS);
mutex_lock(&iqs620_pwm->lock);
@@ -81,7 +82,7 @@ static int iqs620_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
}
if (duty_scale) {
- u8 duty_val = min(duty_scale - 1, 0xFF);
+ u8 duty_val = min_t(u64, duty_scale - 1, 0xff);
ret = regmap_write(iqs62x->regmap, IQS620_PWM_DUTY_CYCLE,
duty_val);