diff options
| author | Eilon Greenstein <eilong@broadcom.com> | 2009-02-12 08:37:14 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2009-02-15 23:31:41 -0800 |
| commit | c2c8b03e200bdda3ba23d27f5c33bac784dced01 (patch) | |
| tree | c15811bb47f3790e106660e5919cb690f288f3af /drivers/net/bnx2x_hsi.h | |
| parent | ed8680a7e68fc07d6b2bfa977e8f5f3d3c568d14 (diff) | |
bnx2x: Pre emphasis configuration
Supporting non-default pre-emphasis settings for the internal and some external
PHYs
Signed-off-by: Yaniv Rosner <yanivr@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2x_hsi.h')
| -rw-r--r-- | drivers/net/bnx2x_hsi.h | 45 |
1 files changed, 15 insertions, 30 deletions
diff --git a/drivers/net/bnx2x_hsi.h b/drivers/net/bnx2x_hsi.h index 7a62bfd18aa8..8452605d0588 100644 --- a/drivers/net/bnx2x_hsi.h +++ b/drivers/net/bnx2x_hsi.h @@ -178,36 +178,21 @@ struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */ u32 rdma_mac_lower; u32 serdes_config; - /* for external PHY, or forced mode or during AN */ -#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0xffff0000 -#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 16 - -#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0x0000ffff -#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 0 - - u16 serdes_tx_driver_pre_emphasis[16]; - u16 serdes_rx_driver_equalizer[16]; - - u32 xgxs_config_lane0; - u32 xgxs_config_lane1; - u32 xgxs_config_lane2; - u32 xgxs_config_lane3; - /* for external PHY, or forced mode or during AN */ -#define PORT_HW_CFG_XGXS_TX_DRV_PRE_EMPHASIS_MASK 0xffff0000 -#define PORT_HW_CFG_XGXS_TX_DRV_PRE_EMPHASIS_SHIFT 16 - -#define PORT_HW_CFG_XGXS_RX_DRV_EQUALIZER_MASK 0x0000ffff -#define PORT_HW_CFG_XGXS_RX_DRV_EQUALIZER_SHIFT 0 - - u16 xgxs_tx_driver_pre_emphasis_lane0[16]; - u16 xgxs_tx_driver_pre_emphasis_lane1[16]; - u16 xgxs_tx_driver_pre_emphasis_lane2[16]; - u16 xgxs_tx_driver_pre_emphasis_lane3[16]; - - u16 xgxs_rx_driver_equalizer_lane0[16]; - u16 xgxs_rx_driver_equalizer_lane1[16]; - u16 xgxs_rx_driver_equalizer_lane2[16]; - u16 xgxs_rx_driver_equalizer_lane3[16]; +#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000FFFF +#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0 + +#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xFFFF0000 +#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16 + + + u32 Reserved0[16]; /* 0x158 */ + + /* for external PHY, or forced mode or during AN */ + u16 xgxs_config_rx[4]; /* 0x198 */ + + u16 xgxs_config_tx[4]; /* 0x1A0 */ + + u32 Reserved1[64]; /* 0x1A8 */ u32 lane_config; #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff |