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authorBernard Zhao <bernard@vivo.com>2020-05-07 04:45:14 -0700
committerKrzysztof Kozlowski <krzk@kernel.org>2020-05-08 16:46:41 +0200
commit4bff7214d263b5235263136cb53147a759b3f3ab (patch)
treeb581945ec82556b3d79c6c8f56d5e592a5a60074 /drivers/memory/samsung
parent8f3d9f354286745c751374f5f1fcafee6b3f3136 (diff)
memory: samsung: exynos5422-dmc: Fix tFAW timings alignment
Aligning of tFAW timing with standard was using wrong argument as minimum acceptable value. This could lead to wrong timing if provided timings and clock period do not match the standard. Fixes: 6e7674c3c6df ("memory: Add DMC driver for Exynos5422") Cc: <stable@vger.kernel.org> Signed-off-by: Bernard Zhao <bernard@vivo.com> Reviewed-by: Lukasz Luba <lukasz.luba@arm.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Diffstat (limited to 'drivers/memory/samsung')
-rw-r--r--drivers/memory/samsung/exynos5422-dmc.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/memory/samsung/exynos5422-dmc.c b/drivers/memory/samsung/exynos5422-dmc.c
index 81a1b1d01683..22a43d662833 100644
--- a/drivers/memory/samsung/exynos5422-dmc.c
+++ b/drivers/memory/samsung/exynos5422-dmc.c
@@ -1091,7 +1091,7 @@ static int create_timings_aligned(struct exynos5_dmc *dmc, u32 *reg_timing_row,
/* power related timings */
val = dmc->timings->tFAW / clk_period_ps;
val += dmc->timings->tFAW % clk_period_ps ? 1 : 0;
- val = max(val, dmc->min_tck->tXP);
+ val = max(val, dmc->min_tck->tFAW);
reg = &timing_power[0];
*reg_timing_power |= TIMING_VAL2REG(reg, val);