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| author | Steve Longerbeam <slongerbeam@gmail.com> | 2014-06-25 18:05:39 -0700 |
|---|---|---|
| committer | Philipp Zabel <p.zabel@pengutronix.de> | 2014-09-02 14:55:47 +0200 |
| commit | a4cd8f229ff71db0c95c0d96381d4fb9239fdb19 (patch) | |
| tree | b9ef78e7375d77ccaf6dc9b3b7e764bde0c5fcdc /drivers/gpu/ipu-v3/ipu-prv.h | |
| parent | 4cea940d34319fb5d5e2f4d554e23f766c228e90 (diff) | |
gpu: ipu-v3: Move IDMAC channel names to imx-ipu-v3.h
Move the IDMAC channel names to imx-ipu-v3.h, to make the names
available outside IPU. Add a couple new channels in the process
(async display BG/FG, channels 24 and 29).
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Diffstat (limited to 'drivers/gpu/ipu-v3/ipu-prv.h')
| -rw-r--r-- | drivers/gpu/ipu-v3/ipu-prv.h | 25 |
1 files changed, 0 insertions, 25 deletions
diff --git a/drivers/gpu/ipu-v3/ipu-prv.h b/drivers/gpu/ipu-v3/ipu-prv.h index 1596a4f52faf..7f08a461c929 100644 --- a/drivers/gpu/ipu-v3/ipu-prv.h +++ b/drivers/gpu/ipu-v3/ipu-prv.h @@ -24,31 +24,6 @@ struct ipu_soc; #include <video/imx-ipu-v3.h> -#define IPUV3_CHANNEL_CSI0 0 -#define IPUV3_CHANNEL_CSI1 1 -#define IPUV3_CHANNEL_CSI2 2 -#define IPUV3_CHANNEL_CSI3 3 -#define IPUV3_CHANNEL_VDI_MEM_IC_VF 5 -#define IPUV3_CHANNEL_MEM_IC_PP 11 -#define IPUV3_CHANNEL_MEM_IC_PRP_VF 12 -#define IPUV3_CHANNEL_G_MEM_IC_PRP_VF 14 -#define IPUV3_CHANNEL_G_MEM_IC_PP 15 -#define IPUV3_CHANNEL_IC_PRP_ENC_MEM 20 -#define IPUV3_CHANNEL_IC_PRP_VF_MEM 21 -#define IPUV3_CHANNEL_IC_PP_MEM 22 -#define IPUV3_CHANNEL_MEM_BG_SYNC 23 -#define IPUV3_CHANNEL_MEM_FG_SYNC 27 -#define IPUV3_CHANNEL_MEM_DC_SYNC 28 -#define IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA 31 -#define IPUV3_CHANNEL_MEM_DC_ASYNC 41 -#define IPUV3_CHANNEL_MEM_ROT_ENC 45 -#define IPUV3_CHANNEL_MEM_ROT_VF 46 -#define IPUV3_CHANNEL_MEM_ROT_PP 47 -#define IPUV3_CHANNEL_ROT_ENC_MEM 48 -#define IPUV3_CHANNEL_ROT_VF_MEM 49 -#define IPUV3_CHANNEL_ROT_PP_MEM 50 -#define IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA 51 - #define IPU_MCU_T_DEFAULT 8 #define IPU_CM_IDMAC_REG_OFS 0x00008000 #define IPU_CM_IC_REG_OFS 0x00020000 |