diff options
| author | Linus Walleij <linus.walleij@linaro.org> | 2017-10-20 14:42:01 +0200 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2017-10-25 11:25:38 +0200 |
| commit | fe29416b5ca2f80b43622ac3023ed9cd0c1ce777 (patch) | |
| tree | b2c61c8ac5438680e96db2c98fba1e10d4d641d6 /drivers/gpio | |
| parent | d97a1b5688b015d94d0365b032c0659957a9e9d1 (diff) | |
gpio: loongson1: fix bgpio usage
When no flags are given, the native endianness is used to access
the MMIO registers, and the pin2mask() call can simply be
converted to a BIT() call, as per the default pin2mask()
implementation in gpio-mmio.c.
Cc: Kelvin Cheung <keguang.zhang@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/gpio')
| -rw-r--r-- | drivers/gpio/gpio-loongson1.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/drivers/gpio/gpio-loongson1.c b/drivers/gpio/gpio-loongson1.c index 72b64039241a..fca84ccac35c 100644 --- a/drivers/gpio/gpio-loongson1.c +++ b/drivers/gpio/gpio-loongson1.c @@ -11,6 +11,7 @@ #include <linux/module.h> #include <linux/gpio/driver.h> #include <linux/platform_device.h> +#include <linux/bitops.h> /* Loongson 1 GPIO Register Definitions */ #define GPIO_CFG 0x0 @@ -22,11 +23,10 @@ static void __iomem *gpio_reg_base; static int ls1x_gpio_request(struct gpio_chip *gc, unsigned int offset) { - unsigned long pinmask = gc->pin2mask(gc, offset); unsigned long flags; spin_lock_irqsave(&gc->bgpio_lock, flags); - __raw_writel(__raw_readl(gpio_reg_base + GPIO_CFG) | pinmask, + __raw_writel(__raw_readl(gpio_reg_base + GPIO_CFG) | BIT(offset), gpio_reg_base + GPIO_CFG); spin_unlock_irqrestore(&gc->bgpio_lock, flags); @@ -35,11 +35,10 @@ static int ls1x_gpio_request(struct gpio_chip *gc, unsigned int offset) static void ls1x_gpio_free(struct gpio_chip *gc, unsigned int offset) { - unsigned long pinmask = gc->pin2mask(gc, offset); unsigned long flags; spin_lock_irqsave(&gc->bgpio_lock, flags); - __raw_writel(__raw_readl(gpio_reg_base + GPIO_CFG) & ~pinmask, + __raw_writel(__raw_readl(gpio_reg_base + GPIO_CFG) & ~BIT(offset), gpio_reg_base + GPIO_CFG); spin_unlock_irqrestore(&gc->bgpio_lock, flags); } |