diff options
| author | Bjorn Andersson <andersson@kernel.org> | 2024-06-20 22:57:26 -0500 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2024-06-21 00:16:28 -0500 |
| commit | 04b1deb821ea7f313d24a9aaf4c592375d688d39 (patch) | |
| tree | f803f0a58a54db76beb84bff67534b6067025b7e /drivers/firmware/qcom | |
| parent | 75287992f58a74271a083fef0356bc81d629f671 (diff) | |
| parent | 81bbb2b891174da9301fc0d4fe9622bd4cb6a995 (diff) | |
Merge branch '20240430-a750-raytracing-v3-2-7f57c5ac082d@gmail.com' into drivers-for-6.11
Merge SMEM and SCM patches related to GPU features through a topic
branch to make it possible to share these with the msm-next DRM tree.
Diffstat (limited to 'drivers/firmware/qcom')
| -rw-r--r-- | drivers/firmware/qcom/qcom_scm.c | 14 | ||||
| -rw-r--r-- | drivers/firmware/qcom/qcom_scm.h | 3 |
2 files changed, 17 insertions, 0 deletions
diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index eb247a83aeeb..c06cbee66327 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -1393,6 +1393,20 @@ int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val, } EXPORT_SYMBOL_GPL(qcom_scm_lmh_dcvsh); +int qcom_scm_gpu_init_regs(u32 gpu_req) +{ + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_GPU, + .cmd = QCOM_SCM_SVC_GPU_INIT_REGS, + .arginfo = QCOM_SCM_ARGS(1), + .args[0] = gpu_req, + .owner = ARM_SMCCC_OWNER_SIP, + }; + + return qcom_scm_call(__scm->dev, &desc, NULL); +} +EXPORT_SYMBOL_GPL(qcom_scm_gpu_init_regs); + static int qcom_scm_find_dload_address(struct device *dev, u64 *addr) { struct device_node *tcsr; diff --git a/drivers/firmware/qcom/qcom_scm.h b/drivers/firmware/qcom/qcom_scm.h index 4532907e8489..484e030bcac9 100644 --- a/drivers/firmware/qcom/qcom_scm.h +++ b/drivers/firmware/qcom/qcom_scm.h @@ -138,6 +138,9 @@ int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc, #define QCOM_SCM_WAITQ_RESUME 0x02 #define QCOM_SCM_WAITQ_GET_WQ_CTX 0x03 +#define QCOM_SCM_SVC_GPU 0x28 +#define QCOM_SCM_SVC_GPU_INIT_REGS 0x01 + /* common error codes */ #define QCOM_SCM_V2_EBUSY -12 #define QCOM_SCM_ENOMEM -5 |