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author | Stephen Boyd <sboyd@kernel.org> | 2019-07-12 11:11:51 -0700 |
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committer | Stephen Boyd <sboyd@kernel.org> | 2019-07-12 11:11:51 -0700 |
commit | b1511f7a48c3ab28ae10b7ea1e9eae1481525bbe (patch) | |
tree | b8e66a9ce155841e4f8ee5f75b386fb83094bc1f /drivers/clk/sunxi | |
parent | 47c9e0cef01494aa512e924b100160206295f45e (diff) | |
parent | 1c099779c1e2e8e0e10cdb2aecd4b35f428e9f00 (diff) | |
parent | 3044a860fd09f02f5609449d93d8ea6084215768 (diff) | |
parent | f9d3fb22ab27aaee8748480fe3fa8cc17875ee30 (diff) | |
parent | 55692cedf3af29039381e3dbf1b598ab21709d1e (diff) |
Merge branches 'clk-bcm63xx', 'clk-silabs', 'clk-lochnagar' and 'clk-rockchip' into clk-next
- Support gated clk controller on MIPS based BCM63XX SoCs
- Small frequency support for SiLabs Si544 chips
- Support SiLabs Si5341 and Si5340 chips
* clk-bcm63xx:
clk: add BCM63XX gated clock controller driver
devicetree: document the BCM63XX gated clock bindings
* clk-silabs:
clk: Add Si5341/Si5340 driver
dt-bindings: clock: Add silabs,si5341
clk: clk-si544: Implement small frequency change support
* clk-lochnagar:
clk: lochnagar: Update DT binding doc to include the primary SPDIF MCLK
clk: lochnagar: Use new parent_data approach to register clock parents
* clk-rockchip:
clk: rockchip: export HDMIPHY clock on rk3228
clk: rockchip: add watchdog pclk on rk3328
clk: rockchip: add clock id for hdmi_phy special clock on rk3228
clk: rockchip: add clock id for watchdog pclk on rk3328
clk: rockchip: convert pclk_wdt boilerplat to new SGRF_GATE macro
clk: rockchip: add a type from SGRF-controlled gate clocks
clk: rockchip: Remove 48 MHz PLL rate from rk3288
clk: rockchip: add 1.464GHz cpu-clock rate to rk3228
clk: rockchip: Slightly more accurate math in rockchip_mmc_get_phase()
clk: rockchip: Don't yell about bad mmc phases when getting
clk: rockchip: Use clk_hw_get_rate() in MMC phase calculation