diff options
| author | Myron Stowe <mstowe@redhat.com> | 2011-10-28 15:48:38 -0600 |
|---|---|---|
| committer | Jesse Barnes <jbarnes@virtuousgeek.org> | 2012-01-06 12:10:42 -0800 |
| commit | 96c5590058d7fded14f43af2ab521436cecf3125 (patch) | |
| tree | 673577f86b1ee8886c27cc86333fdfdc6cc783ac /arch/x86/include/asm/pci_x86.h | |
| parent | 9cdce18d6f0baae53f012fb3f50e66e7ff24c509 (diff) | |
PCI: Pull PCI 'latency timer' setup up into the core
The 'latency timer' of PCI devices, both Type 0 and Type 1,
is setup in architecture-specific code [see: 'pcibios_set_master()'].
There are two approaches being taken by all the architectures - check
if the 'latency timer' is currently set between 16 and 255 and if not
bring it within bounds, or, do nothing (and then there is the
gratuitously different PA-RISC implementation).
There is nothing architecture-specific about PCI's 'latency timer' so
this patch pulls its setup functionality up into the PCI core by
creating a generic 'pcibios_set_master()' function using the '__weak'
attribute which can be used by all architectures as a default which,
if necessary, can then be over-ridden by architecture-specific code.
No functional change.
Signed-off-by: Myron Stowe <myron.stowe@redhat.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'arch/x86/include/asm/pci_x86.h')
| -rw-r--r-- | arch/x86/include/asm/pci_x86.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h index e38197806853..b3a531746026 100644 --- a/arch/x86/include/asm/pci_x86.h +++ b/arch/x86/include/asm/pci_x86.h @@ -44,8 +44,6 @@ enum pci_bf_sort_state { /* pci-i386.c */ -extern unsigned int pcibios_max_latency; - void pcibios_resource_survey(void); void pcibios_set_cache_line_size(void); |