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authorJon Hunter <jonathanh@nvidia.com>2015-06-03 12:43:41 +0100
committerThierry Reding <treding@nvidia.com>2015-09-15 11:22:04 +0200
commit9a0baee960a718b2fde249b7d9197641fb8eb08d (patch)
tree26bbbd7edad666b55d12fa5af47e4f6ea2dae466 /arch/arm/boot/dts/tegra124-nyan.dtsi
parent6ff33f3902c3b1c5d0db6b1e2c70b6d76fba357f (diff)
ARM: tegra: Enable CPUFreq support for Tegra124 Chromebooks
Add the device-tree DFLL clock node and CPU regulator phandle for Tegra124 Chromebooks to enable CPUFreq support on these boards. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra124-nyan.dtsi')
-rw-r--r--arch/arm/boot/dts/tegra124-nyan.dtsi15
1 files changed, 14 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi
index a9aec23e06f2..40c23a0b7cfc 100644
--- a/arch/arm/boot/dts/tegra124-nyan.dtsi
+++ b/arch/arm/boot/dts/tegra124-nyan.dtsi
@@ -159,7 +159,7 @@
vin-ldo9-10-supply = <&vdd_5v0_sys>;
vin-ldo11-supply = <&vdd_3v3_run>;
- sd0 {
+ vdd_cpu: sd0 {
regulator-name = "+VDD_CPU_AP";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1350000>;
@@ -397,6 +397,13 @@
non-removable;
};
+ /* CPU DFLL clock */
+ clock@0,70110000 {
+ status = "okay";
+ vdd-cpu-supply = <&vdd_cpu>;
+ nvidia,i2c-fs-rate = <400000>;
+ };
+
ahub@0,70300000 {
i2s@0,70301100 {
status = "okay";
@@ -487,6 +494,12 @@
};
};
+ cpus {
+ cpu@0 {
+ vdd-cpu-supply = <&vdd_cpu>;
+ };
+ };
+
gpio-keys {
compatible = "gpio-keys";