diff options
| author | Kishon Vijay Abraham I <kishon@ti.com> | 2019-03-25 15:15:25 +0530 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2019-04-09 07:59:12 -0700 |
| commit | b5acec09e259d9972b0e82e3a97ca019f0df29bb (patch) | |
| tree | 7a9aeeafd678d9ab082cb40b2df305caa11ef6eb /arch/arm/boot/dts/dra7.dtsi | |
| parent | 9e98c678c2d6ae3a17cb2de55d17f69dddaa231b (diff) | |
ARM: dts: dra7: Add properties to enable PCIe x2 lane mode
ti,syscon-lane-sel and ti,syscon-lane-conf properties specific to enable
PCIe x2 lane mode are added here.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/dra7.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/dra7.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 2bc9add8b7a5..d87e932f45bd 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -193,6 +193,7 @@ ti,hwmods = "pcie1"; phys = <&pcie1_phy>; phy-names = "pcie-phy0"; + ti,syscon-lane-sel = <&scm_conf_pcie 0x18>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie1_intc 1>, <0 0 0 2 &pcie1_intc 2>, @@ -218,6 +219,7 @@ phys = <&pcie1_phy>; phy-names = "pcie-phy0"; ti,syscon-unaligned-access = <&scm_conf1 0x14 1>; + ti,syscon-lane-sel = <&scm_conf_pcie 0x18>; status = "disabled"; }; }; |