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authorPratyush Yadav <p.yadav@ti.com>2021-05-31 23:47:54 +0530
committerTudor Ambarus <tudor.ambarus@microchip.com>2021-12-23 15:04:13 +0200
commit9de3cb1cc95bc815ff6d29cfe6c5e1f171ac2b09 (patch)
tree20e28aa3c303d2c5a856229afb9cfb65d8abe938 /LICENSES
parent63017068a6d991fdf31147c4996cd29bfde61ac2 (diff)
mtd: spi-nor: micron-st: write 2 bytes when disabling Octal DTR mode
The Octal DTR configuration is stored in the CFR0V register. This register is 1 byte wide. But 1 byte long transactions are not allowed in 8D-8D-8D mode. The next byte address contains the CFR1V register, which contains the number of dummy cycles. This is very fortunate since the enable path changes the value of this register. Reset the value to its default when disabling Octal DTR mode. This way, both changes to the flash state made when enabling can be reverted in one single transaction. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20210531181757.19458-4-p.yadav@ti.com
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