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| author | Samuel Holland <samuel@sholland.org> | 2023-01-26 00:34:18 -0600 |
|---|---|---|
| committer | Jernej Skrabec <jernej.skrabec@gmail.com> | 2023-01-27 23:20:37 +0100 |
| commit | 0e30ca5ab0a80fdc7f1055f63c1436dfdc4d317d (patch) | |
| tree | 8ac5af5dbe4e3ac1ff2c7dbb56befe682eb4ebc2 /Documentation/timers | |
| parent | 84def5abbb5252681bb5aa7e3e253c37b75ed9e7 (diff) | |
soc: sunxi: Add Allwinner D1 PPU driver
The PPU contains a series of identical MMIO register ranges, one for
each power domain. Each range contains control/status bits for a clock
gate, reset line, output gates, and a power switch. (The clock and reset
are separate from, and in addition to, the bits in the CCU.) It also
contains a hardware power sequence engine to control the other bits.
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20230126063419.15971-3-samuel@sholland.org
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Diffstat (limited to 'Documentation/timers')
0 files changed, 0 insertions, 0 deletions