diff options
| author | Tzung-Bi Shih <tzungbi@google.com> | 2021-01-27 16:31:34 +0800 |
|---|---|---|
| committer | Bjorn Andersson <bjorn.andersson@linaro.org> | 2021-02-09 09:08:45 -0600 |
| commit | ff3ea536023e8a40c499f884bdc3cc5aec5b1e25 (patch) | |
| tree | 30bd36366152c8fdf3039101d2784c9663e95784 | |
| parent | 2e88e8fcdfcd2e5569180944789ff299114c2bf7 (diff) | |
remoteproc/mediatek: enable MPU for all memory regions in MT8192 SCP
The register MT8192_CORE0_MEM_ATT_PREDEF contains attributes for each
memory region. It defines whether a memory region can be managed by MPU
or not.
In the past, due to the default settings in the register, MT8192 SCP
works luckily. After enabling L1TCM, SCP starts to access memory region
that is not included in the default settings. As a result, SCP hangs.
Enables MPU for all memory regions in MT8192 SCP.
Note that the register is read only once when SCP resets. Thus, it must
be set from kernel side.
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Tzung-Bi Shih <tzungbi@google.com>
Link: https://lore.kernel.org/r/20210127083136.3745652-3-tzungbi@google.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
| -rw-r--r-- | drivers/remoteproc/mtk_common.h | 1 | ||||
| -rw-r--r-- | drivers/remoteproc/mtk_scp.c | 3 |
2 files changed, 4 insertions, 0 deletions
diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h index bcab38511bf3..204691138677 100644 --- a/drivers/remoteproc/mtk_common.h +++ b/drivers/remoteproc/mtk_common.h @@ -47,6 +47,7 @@ #define MT8192_CORE0_SW_RSTN_CLR 0x10000 #define MT8192_CORE0_SW_RSTN_SET 0x10004 +#define MT8192_CORE0_MEM_ATT_PREDEF 0x10008 #define MT8192_CORE0_WDT_IRQ 0x10030 #define MT8192_CORE0_WDT_CFG 0x10034 diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index d83e1164f02f..05b157689121 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -371,6 +371,9 @@ static int mt8192_scp_before_load(struct mtk_scp *scp) mt8192_power_on_sram(scp->reg_base + MT8192_L1TCM_SRAM_PDN); mt8192_power_on_sram(scp->reg_base + MT8192_CPU0_SRAM_PD); + /* enable MPU for all memory regions */ + writel(0xff, scp->reg_base + MT8192_CORE0_MEM_ATT_PREDEF); + return 0; } |