diff options
| author | Samuel Holland <samuel@sholland.org> | 2022-06-14 23:55:43 -0500 |
|---|---|---|
| committer | Maxime Ripard <maxime@cerno.tech> | 2022-06-16 09:27:46 +0200 |
| commit | 6da623684cdbe4532c55ed7f18b9b46badb730cd (patch) | |
| tree | 2448878fd4a2d664cd002bb3020215f5b638a4e4 | |
| parent | ef2731e48b51857840f59d168d18d2f1e862b1b7 (diff) | |
drm/sun4i: sun8i-hdmi-phy: Group PHY ops functions by generation
Now that the PHY ops are separated, sort them topologically, with the
common sun8i_hdmi_phy_set_polarity helper at the top. No function
contents are changed in this commit.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20220615045543.62813-7-samuel@sholland.org
| -rw-r--r-- | drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 67 |
1 files changed, 32 insertions, 35 deletions
diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c index f94c1ddddbad..ca53b5e9fffc 100644 --- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c +++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c @@ -124,7 +124,19 @@ static const struct dw_hdmi_phy_config sun50i_h6_phy_config[] = { }; static void sun8i_hdmi_phy_set_polarity(struct sun8i_hdmi_phy *phy, - const struct drm_display_mode *mode); + const struct drm_display_mode *mode) +{ + u32 val = 0; + + if (mode->flags & DRM_MODE_FLAG_NHSYNC) + val |= SUN8I_HDMI_PHY_DBG_CTRL_POL_NHSYNC; + + if (mode->flags & DRM_MODE_FLAG_NVSYNC) + val |= SUN8I_HDMI_PHY_DBG_CTRL_POL_NVSYNC; + + regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG, + SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK, val); +}; static int sun8i_a83t_hdmi_phy_config(struct dw_hdmi *hdmi, void *data, const struct drm_display_info *display, @@ -193,6 +205,25 @@ static int sun8i_a83t_hdmi_phy_config(struct dw_hdmi *hdmi, void *data, return 0; } +static void sun8i_a83t_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) +{ + struct sun8i_hdmi_phy *phy = data; + + dw_hdmi_phy_gen2_txpwron(hdmi, 0); + dw_hdmi_phy_gen2_pddq(hdmi, 1); + + regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG, + SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN, 0); +} + +static const struct dw_hdmi_phy_ops sun8i_a83t_hdmi_phy_ops = { + .init = sun8i_a83t_hdmi_phy_config, + .disable = sun8i_a83t_hdmi_phy_disable, + .read_hpd = dw_hdmi_phy_read_hpd, + .update_hpd = dw_hdmi_phy_update_hpd, + .setup_hpd = dw_hdmi_phy_setup_hpd, +}; + static int sun8i_h3_hdmi_phy_config(struct dw_hdmi *hdmi, void *data, const struct drm_display_info *display, const struct drm_display_mode *mode) @@ -348,32 +379,6 @@ static int sun8i_h3_hdmi_phy_config(struct dw_hdmi *hdmi, void *data, return 0; } -static void sun8i_hdmi_phy_set_polarity(struct sun8i_hdmi_phy *phy, - const struct drm_display_mode *mode) -{ - u32 val = 0; - - if (mode->flags & DRM_MODE_FLAG_NHSYNC) - val |= SUN8I_HDMI_PHY_DBG_CTRL_POL_NHSYNC; - - if (mode->flags & DRM_MODE_FLAG_NVSYNC) - val |= SUN8I_HDMI_PHY_DBG_CTRL_POL_NVSYNC; - - regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG, - SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK, val); -}; - -static void sun8i_a83t_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) -{ - struct sun8i_hdmi_phy *phy = data; - - dw_hdmi_phy_gen2_txpwron(hdmi, 0); - dw_hdmi_phy_gen2_pddq(hdmi, 1); - - regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG, - SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN, 0); -} - static void sun8i_h3_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) { struct sun8i_hdmi_phy *phy = data; @@ -385,14 +390,6 @@ static void sun8i_h3_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) regmap_write(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, 0); } -static const struct dw_hdmi_phy_ops sun8i_a83t_hdmi_phy_ops = { - .init = sun8i_a83t_hdmi_phy_config, - .disable = sun8i_a83t_hdmi_phy_disable, - .read_hpd = dw_hdmi_phy_read_hpd, - .update_hpd = dw_hdmi_phy_update_hpd, - .setup_hpd = dw_hdmi_phy_setup_hpd, -}; - static const struct dw_hdmi_phy_ops sun8i_h3_hdmi_phy_ops = { .init = sun8i_h3_hdmi_phy_config, .disable = sun8i_h3_hdmi_phy_disable, |