diff options
| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2016-03-29 11:08:22 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2016-04-01 23:27:47 +0100 |
| commit | 0fc03d4c87611cefa4df10404a7e0df49b0a2132 (patch) | |
| tree | 5e33af3bf03f264863b65906680db6a2ca4e4b35 | |
| parent | f55532a0c0b8bb6148f4e07853b876ef73bc69ca (diff) | |
ARM: SMP enable of cache maintanence broadcast
Masahiro Yamada reports that we can fail to set the FW bit in the
auxiliary control register, which enables broadcasting the cache
maintanence operations. This occurs because we only check that the
SMP/nAMP bit is set, rather than checking whether all the bits we
want to be set are set.
Rearrange the code to ensure that all desired bits are set, and only
update the register if we discover some required bits are not set.
Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| -rw-r--r-- | arch/arm/mm/proc-v7.S | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 0f8963a7e7d9..6fcaac8e200f 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -281,12 +281,12 @@ __v7_ca17mp_setup: bl v7_invalidate_l1 ldmia r12, {r1-r6, lr} #ifdef CONFIG_SMP + orr r10, r10, #(1 << 6) @ Enable SMP/nAMP mode ALT_SMP(mrc p15, 0, r0, c1, c0, 1) - ALT_UP(mov r0, #(1 << 6)) @ fake it for UP - tst r0, #(1 << 6) @ SMP/nAMP mode enabled? - orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode - orreq r0, r0, r10 @ Enable CPU-specific SMP bits - mcreq p15, 0, r0, c1, c0, 1 + ALT_UP(mov r0, r10) @ fake it for UP + orr r10, r10, r0 @ Set required bits + teq r10, r0 @ Were they already set? + mcrne p15, 0, r10, c1, c0, 1 @ No, update register #endif b __v7_setup_cont |