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path: root/drivers/gpu/drm/i915/display/intel_dvo.c
AgeCommit message (Expand)AuthorFilesLines
2023-12-05drm/i915: Skip some timing checks on BXT/GLK DSI transcodersVille Syrjälä1-0/+6
2023-10-04drm/i915: convert INTEL_DISPLAY_ENABLED() into a functionJani Nikula1-1/+1
2023-09-15drm/i915/dvo: Populate connector->ddcVille Syrjälä1-6/+5
2023-06-20drm/i915: Assert that the port being initialized is validVille Syrjälä1-0/+2
2023-05-05drm/i915/display: Add new member to configure PCON color conversionAnkit Nautiyal1-0/+1
2023-02-16drm/i915/display/misc: use intel_de_rmw if possibleAndrzej Hajda1-5/+2
2023-01-26drm/i915/panel: move panel fixed EDID to struct intel_panelJani Nikula1-1/+1
2022-11-23drm/i915/dvo: Log about what was detected on which DVO portVille Syrjälä1-0/+4
2022-11-23drm/i915/dvo: Extract intel_dvo_regs.hVille Syrjälä1-0/+1
2022-11-23drm/i915/dvo: Use intel_de_rmw() for DVO enable/disableVille Syrjälä1-6/+5
2022-11-23drm/i915/dvo: Use REG_BIT() & co. for DVO registersVille Syrjälä1-3/+4
2022-11-23drm/i915/dvo: Rename the "active data order" bitsVille Syrjälä1-2/+2
2022-11-23drm/i915/dvo: Define a few more DVO register bitsVille Syrjälä1-1/+2
2022-11-23drm/i915/dvo: Parametrize DVO/DVO_SRCDIM registersVille Syrjälä1-45/+28
2022-11-19drm/i915/dvo: Use per device debugsVille Syrjälä1-2/+2
2022-11-19drm/i915/dvo: s/dev_priv/i915/Ville Syrjälä1-27/+26
2022-11-19drm/i915/dvo: s/intel_encoder/encoder/ etc.Ville Syrjälä1-46/+45
2022-11-19drm/i915/dvo: Flatten intel_dvo_init()Ville Syrjälä1-100/+117
2022-11-19drm/i915/dvo: Eliminate useless 'port' variableVille Syrjälä1-8/+6
2022-11-19drm/i915/dvo: Introduce intel_dvo_connector_type()Ville Syrjälä1-13/+19
2022-11-19drm/i915/dvo: Actually initialize the DVO encoder typeVille Syrjälä1-4/+16
2022-11-19drm/i915/dvo: Don't leak connector state on DVO init failureVille Syrjälä1-1/+1
2022-11-19drm/i915/dvo: Remove unused panel_wants_ditherVille Syrjälä1-4/+0
2022-11-11drm/i915: stop including i915_irq.h from i915_trace.hJani Nikula1-0/+1
2022-09-26drm/i915: Clean up connector->*_allowed setupVille Syrjälä1-2/+0
2022-09-26drm/i915: Use BIT() when dealing with output typesVille Syrjälä1-2/+2
2022-03-31drm/i915: Put fixed modes directly onto the panel's fixed_modes listVille Syrjälä1-5/+4
2022-03-29drm/i915: Extract intel_panel_encoder_fixed_mode()Ville Syrjälä1-24/+6
2022-03-29drm/i915: Use DRM_MODE_FMT+DRM_MODE_ARG()Ville Syrjälä1-2/+2
2022-03-29drm/i915: Pass intel_connector to intel_panel_{init,fini}()Ville Syrjälä1-1/+1
2022-03-15drm/i915: Introduce intel_panel_get_modes()Ville Syrjälä1-13/+1
2022-03-15drm/i915: Introduce intel_panel_{fixed,downclock}_mode()Ville Syrjälä1-3/+3
2021-09-30drm/i915: Introduce intel_panel_compute_config()Ville Syrjälä1-2/+8
2021-09-30drm/i915: Use intel_panel_mode_valid() for DSI/LVDS/(s)DVOVille Syrjälä1-6/+8
2021-08-26drm/i915/panel: mass rename functions to have intel_panel_ prefixJani Nikula1-1/+1
2021-05-05drm/i915: Don't include intel_de.h from intel_display_types.hVille Syrjälä1-0/+1
2020-12-02drm/i915: remove last traces of I915_READ(), I915_WRITE() and POSTING_READ()Jani Nikula1-4/+0
2020-09-15drm/i915: Reduce INTEL_DISPLAY_ENABLED to just treat outputs as disconnectedVille Syrjälä1-0/+6
2020-07-09drm/i915/dvo: Make .get_modes() return the number of modesVille Syrjälä1-6/+8
2020-04-03drm/i915: Pass atomic state to encoder hooksVille Syrjälä1-3/+6
2020-02-27drm/i915: significantly reduce the use of <drm/i915_drm.h>Jani Nikula1-1/+0
2020-02-04drm/i915/dvo: Mark TMDS DVO connectors as polledVille Syrjälä1-0/+2
2020-02-04drm/i915: Mark ns2501 as LVDS without a fixed modeVille Syrjälä1-5/+8
2020-01-27drm/i915/dvo: use intel_de_*() functions for register accessJani Nikula1-17/+17
2020-01-13drm/i915: Pass intel_connector to intel_attached_*()Ville Syrjälä1-4/+4
2019-11-01drm/i915: Perform automated conversions for crtc uapi/hw split, base -> uapi.Maarten Lankhorst1-1/+1
2019-11-01drm/i915: Perform automated conversions for crtc uapi/hw split, base -> hw.Maarten Lankhorst1-6/+6
2019-10-31drm/i915: Simplify pipe_mask setup even furtherVille Syrjälä1-1/+1
2019-10-31drm/i915: s/crtc_mask/pipe_mask/Ville Syrjälä1-1/+1
2019-10-02drm/i915: Clean up encoder->crtc_mask setupVille Syrjälä1-1/+1
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