summaryrefslogtreecommitdiff
path: root/lib/lcm.c
diff options
context:
space:
mode:
authorMarc Zyngier <marc.zyngier@arm.com>2015-09-13 12:14:32 +0100
committerThomas Gleixner <tglx@linutronix.de>2015-09-15 17:06:29 +0200
commit5a9a8915c8888b615521b17d70a4342187eae60b (patch)
treec07f12f39a4e6ad2cabacc50d6d6e548406b1ab3 /lib/lcm.c
parent12e14066f4835f5ee1ca795f0309415b54c067a9 (diff)
irqchip/gic-v3-its: Add missing cache flushes
When the ITS is configured for non-cacheable transactions, make sure that the allocated, zeroed memory is flushed to the Point of Coherency, allowing the ITS to observe the zeros instead of random garbage (or even get its own data overwritten by zeros being evicted from the cache...). Fixes: 241a386c7dbb "irqchip: gicv3-its: Use non-cacheable accesses when no shareability" Reported-and-tested-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: Pavel Fedin <p.fedin@samsung.com> Cc: Jason Cooper <jason@lakedaemon.net> Link: http://lkml.kernel.org/r/1442142873-20213-3-git-send-email-marc.zyngier@arm.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'lib/lcm.c')
0 files changed, 0 insertions, 0 deletions