diff options
| author | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2019-02-08 10:24:13 -0600 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2019-04-23 16:38:09 -0500 |
| commit | f873c51a155aaa6dafdc00fa7fda3754f2f9f794 (patch) | |
| tree | 88bbcafe510c39f18542f311fd42b9be2a68bbce /include/linux/pci_hotplug.h | |
| parent | 87fcf12e846a5028c14d21a94a0712fd1ad5bad0 (diff) | |
PCI/ACPI: Implement _HPX Type 3 Setting Record
The _HPX Type 3 Setting Record is intended to be more generic and allow
configuration of settings not possible with Type 2 records. For example,
firmware could ensure that the completion timeout value is set accordingly
throughout the PCI tree.
Implement support for _HPX Type 3 Setting Records, which were added in the
ACPI 6.3 spec.
Link: https://lore.kernel.org/lkml/20190208162414.3996-4-mr.nuke.me@gmail.com
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'include/linux/pci_hotplug.h')
| -rw-r--r-- | include/linux/pci_hotplug.h | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/include/linux/pci_hotplug.h b/include/linux/pci_hotplug.h index 2c1e12b7ac00..f694eb2ca978 100644 --- a/include/linux/pci_hotplug.h +++ b/include/linux/pci_hotplug.h @@ -124,10 +124,58 @@ struct hpp_type2 { u32 sec_unc_err_mask_or; }; +/* + * _HPX PCI Express Setting Record (Type 3) + */ +struct hpx_type3 { + u16 device_type; + u16 function_type; + u16 config_space_location; + u16 pci_exp_cap_id; + u16 pci_exp_cap_ver; + u16 pci_exp_vendor_id; + u16 dvsec_id; + u16 dvsec_rev; + u16 match_offset; + u32 match_mask_and; + u32 match_value; + u16 reg_offset; + u32 reg_mask_and; + u32 reg_mask_or; +}; + struct hotplug_program_ops { void (*program_type0)(struct pci_dev *dev, struct hpp_type0 *hpp); void (*program_type1)(struct pci_dev *dev, struct hpp_type1 *hpp); void (*program_type2)(struct pci_dev *dev, struct hpp_type2 *hpp); + void (*program_type3)(struct pci_dev *dev, struct hpx_type3 *hpp); +}; + +enum hpx_type3_dev_type { + HPX_TYPE_ENDPOINT = BIT(0), + HPX_TYPE_LEG_END = BIT(1), + HPX_TYPE_RC_END = BIT(2), + HPX_TYPE_RC_EC = BIT(3), + HPX_TYPE_ROOT_PORT = BIT(4), + HPX_TYPE_UPSTREAM = BIT(5), + HPX_TYPE_DOWNSTREAM = BIT(6), + HPX_TYPE_PCI_BRIDGE = BIT(7), + HPX_TYPE_PCIE_BRIDGE = BIT(8), +}; + +enum hpx_type3_fn_type { + HPX_FN_NORMAL = BIT(0), + HPX_FN_SRIOV_PHYS = BIT(1), + HPX_FN_SRIOV_VIRT = BIT(2), +}; + +enum hpx_type3_cfg_loc { + HPX_CFG_PCICFG = 0, + HPX_CFG_PCIE_CAP = 1, + HPX_CFG_PCIE_CAP_EXT = 2, + HPX_CFG_VEND_CAP = 3, + HPX_CFG_DVSEC = 4, + HPX_CFG_MAX, }; #ifdef CONFIG_ACPI |