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authorLinus Torvalds <torvalds@woody.linux-foundation.org>2007-10-11 19:21:23 -0700
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-10-11 19:21:23 -0700
commitdd6d1844af33acb4edd0a40b1770d091a22c94be (patch)
treee6bd3549919773a13b770324a4dddb51b194b452 /include/asm-mips/mach-mipssim/war.h
parent19f71153b9be219756c6b2757921433a69b7975c (diff)
parentaaf76a3245c02faba51c96b9a340c14d6bb0dcc0 (diff)
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (80 commits) [MIPS] tlbex.c: Cleanup __init usage. [MIPS] WRPPMC serial support move to platform device [MIPS] R1: Fix hazard barriers to make kernels work on R2 also. [MIPS] VPE: reimplement ELF loader. [MIPS] cleanup WRPPMC include files [MIPS] Add BUG_ON assertion for attempt to run kernel on the wrong CPU type. [MIPS] SMP: Use ISO C struct initializer for local structs. [MIPS] SMP: Kill useless casts. [MIPS] Kill num_online_cpus() loops. [MIPS] SMP: Implement smp_call_function_mask(). [MIPS] Make facility to convert CPU types to strings generally available. [MIPS] Convert list of CPU types from #define to enum. [MIPS] Optimize get_unaligned / put_unaligned implementations. [MIPS] checkfiles: Fix "need space after that ','" errors. [MIPS] Fix "no space between function name and open parenthesis" warnings. [MIPS] Allow hardwiring of the CPU type to a single type for optimization. [MIPS] tlbex: Size optimize code by declaring a few functions inline. [MIPS] pg-r4k.c: Dump the generated code [MIPS] Cobalt: Remove cobalt_machine_power_off() [MIPS] Cobalt: Move reset port definition to arch/mips/cobalt/reset.c ...
Diffstat (limited to 'include/asm-mips/mach-mipssim/war.h')
-rw-r--r--include/asm-mips/mach-mipssim/war.h25
1 files changed, 25 insertions, 0 deletions
diff --git a/include/asm-mips/mach-mipssim/war.h b/include/asm-mips/mach-mipssim/war.h
new file mode 100644
index 000000000000..c8a74a3515e0
--- /dev/null
+++ b/include/asm-mips/mach-mipssim/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_MIPSSIM_WAR_H
+#define __ASM_MIPS_MACH_MIPSSIM_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR 0
+#define R4600_V1_HIT_CACHEOP_WAR 0
+#define R4600_V2_HIT_CACHEOP_WAR 0
+#define R5432_CP0_INTERRUPT_WAR 0
+#define BCM1250_M3_WAR 0
+#define SIBYTE_1956_WAR 0
+#define MIPS4K_ICACHE_REFILL_WAR 0
+#define MIPS_CACHE_SYNC_WAR 0
+#define TX49XX_ICACHE_INDEX_INV_WAR 0
+#define RM9000_CDEX_SMP_WAR 0
+#define ICACHE_REFILLS_WORKAROUND_WAR 0
+#define R10000_LLSC_WAR 0
+#define MIPS34K_MISSED_ITLB_WAR 0
+
+#endif /* __ASM_MIPS_MACH_MIPSSIM_WAR_H */