diff options
| author | Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> | 2009-07-03 16:08:24 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2009-09-15 12:01:39 -0700 |
| commit | 9f7f00cd28e9f3bc578eb41489f4a75cf17fbdc8 (patch) | |
| tree | 340d3ec10c16901166af7d0b57f9ff9eecb635af /drivers/staging/rtl8192su | |
| parent | 0f29f5871c165e346409f62d903f97cfad3894c5 (diff) | |
Staging: rtl8192su: remove unused files
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/staging/rtl8192su')
| -rw-r--r-- | drivers/staging/rtl8192su/r8190_rtl8256.c | 312 | ||||
| -rw-r--r-- | drivers/staging/rtl8192su/r8192U_hw.h | 746 | ||||
| -rw-r--r-- | drivers/staging/rtl8192su/r819xU_firmware.c | 697 | ||||
| -rw-r--r-- | drivers/staging/rtl8192su/r819xU_firmware.h | 106 | ||||
| -rw-r--r-- | drivers/staging/rtl8192su/r819xU_phy.c | 1808 | ||||
| -rw-r--r-- | drivers/staging/rtl8192su/r819xU_phy.h | 90 | ||||
| -rw-r--r-- | drivers/staging/rtl8192su/r819xU_phyreg.h | 871 |
7 files changed, 0 insertions, 4630 deletions
diff --git a/drivers/staging/rtl8192su/r8190_rtl8256.c b/drivers/staging/rtl8192su/r8190_rtl8256.c deleted file mode 100644 index 74ff337b0583..000000000000 --- a/drivers/staging/rtl8192su/r8190_rtl8256.c +++ /dev/null @@ -1,312 +0,0 @@ -/* - This is part of the rtl8192 driver - released under the GPL (See file COPYING for details). - - This files contains programming code for the rtl8256 - radio frontend. - - *Many* thanks to Realtek Corp. for their great support! - -*/ - -#include "r8192U.h" -#include "r8192U_hw.h" -#include "r819xU_phyreg.h" -#include "r819xU_phy.h" -#include "r8190_rtl8256.h" - -/*-------------------------------------------------------------------------- - * Overview: set RF band width (20M or 40M) - * Input: struct net_device* dev - * WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M - * Output: NONE - * Return: NONE - * Note: 8226 support both 20M and 40 MHz - *---------------------------------------------------------------------------*/ -void PHY_SetRF8256Bandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth) //20M or 40M -{ - u8 eRFPath; - struct r8192_priv *priv = ieee80211_priv(dev); - - //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++) - for(eRFPath = 0; eRFPath <RF90_PATH_MAX; eRFPath++) - { - if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) - continue; - - switch(Bandwidth) - { - case HT_CHANNEL_WIDTH_20: - if(priv->card_8192_version == VERSION_819xU_A || priv->card_8192_version == VERSION_819xU_B)// 8256 D-cut, E-cut, xiong: consider it later! - { - rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x100); //phy para:1ba - rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3d7); - rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x021); - - //cosa add for sd3's request 01/23/2008 - rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x5ab); - } - else - { - RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n"); - } - - break; - case HT_CHANNEL_WIDTH_20_40: - if(priv->card_8192_version == VERSION_819xU_A ||priv->card_8192_version == VERSION_819xU_B)// 8256 D-cut, E-cut, xiong: consider it later! - { - rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x300); //phy para:3ba - rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3df); - rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x0a1); - - //cosa add for sd3's request 01/23/2008 - if(priv->chan == 3 || priv->chan == 9) //I need to set priv->chan whenever current channel changes - rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x59b); - else - rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x5ab); - } - else - { - RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n"); - } - - - break; - default: - RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth ); - break; - - } - } - return; -} -/*-------------------------------------------------------------------------- - * Overview: Interface to config 8256 - * Input: struct net_device* dev - * Output: NONE - * Return: NONE - *---------------------------------------------------------------------------*/ -void PHY_RF8256_Config(struct net_device* dev) -{ - struct r8192_priv *priv = ieee80211_priv(dev); - // Initialize general global value - // - // TODO: Extend RF_PATH_C and RF_PATH_D in the future - priv->NumTotalRFPath = RTL819X_TOTAL_RF_PATH; - // Config BB and RF - phy_RF8256_Config_ParaFile(dev); - - return; -} -/*-------------------------------------------------------------------------- - * Overview: Interface to config 8256 - * Input: struct net_device* dev - * Output: NONE - * Return: NONE - *---------------------------------------------------------------------------*/ -void phy_RF8256_Config_ParaFile(struct net_device* dev) -{ - u32 u4RegValue = 0; - //static s1Byte szRadioAFile[] = RTL819X_PHY_RADIO_A; - //static s1Byte szRadioBFile[] = RTL819X_PHY_RADIO_B; - //static s1Byte szRadioCFile[] = RTL819X_PHY_RADIO_C; - //static s1Byte szRadioDFile[] = RTL819X_PHY_RADIO_D; - u8 eRFPath; - BB_REGISTER_DEFINITION_T *pPhyReg; - struct r8192_priv *priv = ieee80211_priv(dev); - u32 RegOffSetToBeCheck = 0x3; - u32 RegValueToBeCheck = 0x7f1; - u32 RF3_Final_Value = 0; - u8 ConstRetryTimes = 5, RetryTimes = 5; - u8 ret = 0; - //3//----------------------------------------------------------------- - //3// <2> Initialize RF - //3//----------------------------------------------------------------- - for(eRFPath = (RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath <priv->NumTotalRFPath; eRFPath++) - { - if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) - continue; - - pPhyReg = &priv->PHYRegDef[eRFPath]; - - // Joseph test for shorten RF config - // pHalData->RfReg0Value[eRFPath] = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, rGlobalCtrl, bMaskDWord); - - /*----Store original RFENV control type----*/ - switch(eRFPath) - { - case RF90_PATH_A: - case RF90_PATH_C: - u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV); - break; - case RF90_PATH_B : - case RF90_PATH_D: - u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16); - break; - } - - /*----Set RF_ENV enable----*/ - rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1); - - /*----Set RF_ENV output high----*/ - rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); - - /* Set bit number of Address and Data for RF register */ - rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 0 to 4 bits for Z-serial and set 1 to 6 bits for 8258 - rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for Z-serial and 8258, and set 1 to 14 bits for ??? - - rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E) eRFPath, 0x0, bMask12Bits, 0xbf); - - /*----Check RF block (for FPGA platform only)----*/ - // TODO: this function should be removed on ASIC , Emily 2007.2.2 - if (rtl8192_phy_checkBBAndRF(dev, HW90_BLOCK_RF, (RF90_RADIO_PATH_E)eRFPath)) - { - RT_TRACE(COMP_ERR, "PHY_RF8256_Config():Check Radio[%d] Fail!!\n", eRFPath); - goto phy_RF8256_Config_ParaFile_Fail; - } - - RetryTimes = ConstRetryTimes; - RF3_Final_Value = 0; - /*----Initialize RF fom connfiguration file----*/ - switch(eRFPath) - { - case RF90_PATH_A: - while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0) - { - ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath); - RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits); - RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); - RetryTimes--; - } - break; - case RF90_PATH_B: - while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0) - { - ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath); - RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits); - RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); - RetryTimes--; - } - break; - case RF90_PATH_C: - while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0) - { - ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath); - RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits); - RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); - RetryTimes--; - } - break; - case RF90_PATH_D: - while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0) - { - ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath); - RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits); - RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); - RetryTimes--; - } - break; - } - - /*----Restore RFENV control type----*/; - switch(eRFPath) - { - case RF90_PATH_A: - case RF90_PATH_C: - rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); - break; - case RF90_PATH_B : - case RF90_PATH_D: - rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue); - break; - } - - if(ret){ - RT_TRACE(COMP_ERR, "phy_RF8256_Config_ParaFile():Radio[%d] Fail!!", eRFPath); - goto phy_RF8256_Config_ParaFile_Fail; - } - - } - - RT_TRACE(COMP_PHY, "PHY Initialization Success\n") ; - return ; - -phy_RF8256_Config_ParaFile_Fail: - RT_TRACE(COMP_ERR, "PHY Initialization failed\n") ; - return ; -} - - -void PHY_SetRF8256CCKTxPower(struct net_device* dev, u8 powerlevel) -{ - u32 TxAGC=0; - struct r8192_priv *priv = ieee80211_priv(dev); - //modified by vivi, 20080109 - TxAGC = powerlevel; - - if(priv->bDynamicTxLowPower == TRUE ) //cosa 05/22/2008 for scan - { - if(priv->CustomerID == RT_CID_819x_Netcore) - TxAGC = 0x22; - else - TxAGC += priv->CckPwEnl; - } - - if(TxAGC > 0x24) - TxAGC = 0x24; - rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC); -} - - -void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel) -{ - struct r8192_priv *priv = ieee80211_priv(dev); - //Joseph TxPower for 8192 testing - u32 writeVal, powerBase0, powerBase1, writeVal_tmp; - u8 index = 0; - u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c}; - u8 byte0, byte1, byte2, byte3; - - powerBase0 = powerlevel + priv->TxPowerDiff; //OFDM rates - powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0; - powerBase1 = powerlevel; //MCS rates - powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1; - - for(index=0; index<6; index++) - { - writeVal = priv->MCSTxPowerLevelOriginalOffset[index] + ((index<2)?powerBase0:powerBase1); - byte0 = (u8)(writeVal & 0x7f); - byte1 = (u8)((writeVal & 0x7f00)>>8); - byte2 = (u8)((writeVal & 0x7f0000)>>16); - byte3 = (u8)((writeVal & 0x7f000000)>>24); - if(byte0 > 0x24) // Max power index = 0x24 - byte0 = 0x24; - if(byte1 > 0x24) - byte1 = 0x24; - if(byte2 > 0x24) - byte2 = 0x24; - if(byte3 > 0x24) - byte3 = 0x24; - - //for tx power track - if(index == 3) - { - writeVal_tmp = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0; - priv->Pwr_Track = writeVal_tmp; - } - - if(priv->bDynamicTxHighPower == TRUE) //Add by Jacken 2008/03/06 - { - // Emily, 20080613. Set low tx power for both MCS and legacy OFDM - writeVal = 0x03030303; - } - else - { - writeVal = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0; - } - rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal); - } - return; - -} - diff --git a/drivers/staging/rtl8192su/r8192U_hw.h b/drivers/staging/rtl8192su/r8192U_hw.h deleted file mode 100644 index f2500e654a79..000000000000 --- a/drivers/staging/rtl8192su/r8192U_hw.h +++ /dev/null @@ -1,746 +0,0 @@ -/* - This is part of rtl8187 OpenSource driver. - Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it> - Released under the terms of GPL (General Public Licence) - - Parts of this driver are based on the GPL part of the - official Realtek driver. - Parts of this driver are based on the rtl8180 driver skeleton - from Patric Schenke & Andres Salomon. - Parts of this driver are based on the Intel Pro Wireless - 2100 GPL driver. - - We want to tanks the Authors of those projects - and the Ndiswrapper project Authors. -*/ - -/* Mariusz Matuszek added full registers definition with Realtek's name */ - -/* this file contains register definitions for the rtl8187 MAC controller */ -#ifndef R8192_HW -#define R8192_HW - -typedef enum _VERSION_819xU{ - VERSION_819xU_A, // A-cut - VERSION_819xU_B, // B-cut - VERSION_819xU_C,// C-cut -}VERSION_819xU,*PVERSION_819xU; -//added for different RF type -typedef enum _RT_RF_TYPE_DEF -{ - RF_1T2R = 0, - RF_2T4R, - - RF_819X_MAX_TYPE -}RT_RF_TYPE_DEF; - - -typedef enum _BaseBand_Config_Type{ - BaseBand_Config_PHY_REG = 0, //Radio Path A - BaseBand_Config_AGC_TAB = 1, //Radio Path B -}BaseBand_Config_Type, *PBaseBand_Config_Type; -#if 0 -typedef enum _RT_RF_TYPE_819xU{ - RF_TYPE_MIN = 0, - RF_8225, - RF_8256, - RF_8258, - RF_PSEUDO_11N = 4, -}RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU; -#endif -#define RTL8187_REQT_READ 0xc0 -#define RTL8187_REQT_WRITE 0x40 -#define RTL8187_REQ_GET_REGS 0x05 -#define RTL8187_REQ_SET_REGS 0x05 - -#define MAX_TX_URB 16 //less URB will cause 2.4.31 crash, need to fix it further -#define MAX_RX_URB 16 - -#define R8180_MAX_RETRY 255 -//#define MAX_RX_NORMAL_URB 3 -//#define MAX_RX_COMMAND_URB 2 -#define RX_URB_SIZE 9100 - -#define BB_ANTATTEN_CHAN14 0x0c -#define BB_ANTENNA_B 0x40 - -#define BB_HOST_BANG (1<<30) -#define BB_HOST_BANG_EN (1<<2) -#define BB_HOST_BANG_CLK (1<<1) -#define BB_HOST_BANG_RW (1<<3) -#define BB_HOST_BANG_DATA 1 - -//#if (RTL819X_FPGA_VER & RTL819X_FPGA_VIVI_070920) -#define AFR 0x010 -#define AFR_CardBEn (1<<0) -#define AFR_CLKRUN_SEL (1<<1) -#define AFR_FuncRegEn (1<<2) -#define RTL8190_EEPROM_ID 0x8129 -#define EEPROM_VID 0x02 -#define EEPROM_PID 0x04 -#define EEPROM_NODE_ADDRESS_BYTE_0 0x0C - -#define EEPROM_TxPowerDiff 0x1F -#define EEPROM_ThermalMeter 0x20 -#define EEPROM_PwDiff 0x21 //0x21 -#define EEPROM_CrystalCap 0x22 //0x22 - -#define EEPROM_TxPwIndex_CCK 0x23 //0x23 -#define EEPROM_TxPwIndex_OFDM_24G 0x24 //0x24~0x26 -#define EEPROM_TxPwIndex_CCK_V1 0x29 //0x29~0x2B -#define EEPROM_TxPwIndex_OFDM_24G_V1 0x2C //0x2C~0x2E -#define EEPROM_TxPwIndex_Ver 0x27 //0x27 - -#define EEPROM_Default_TxPowerDiff 0x0 -#define EEPROM_Default_ThermalMeter 0x7 -#define EEPROM_Default_PwDiff 0x4 -#define EEPROM_Default_CrystalCap 0x5 -#define EEPROM_Default_TxPower 0x1010 -#define EEPROM_Customer_ID 0x7B //0x7B:CustomerID -#define EEPROM_ChannelPlan 0x16 //0x7C -#define EEPROM_IC_VER 0x7d //0x7D -#define EEPROM_CRC 0x7e //0x7E~0x7F - -#define EEPROM_CID_DEFAULT 0x0 -#define EEPROM_CID_CAMEO 0x1 -#define EEPROM_CID_RUNTOP 0x2 -#define EEPROM_CID_Senao 0x3 -#define EEPROM_CID_TOSHIBA 0x4 // Toshiba setting, Merge by Jacken, 2008/01/31 -#define EEPROM_CID_NetCore 0x5 -#define EEPROM_CID_Nettronix 0x6 -#define EEPROM_CID_Pronet 0x7 -#define EEPROM_CID_DLINK 0x8 - -#define AC_PARAM_TXOP_LIMIT_OFFSET 16 -#define AC_PARAM_ECW_MAX_OFFSET 12 -#define AC_PARAM_ECW_MIN_OFFSET 8 -#define AC_PARAM_AIFS_OFFSET 0 - -//#endif -enum _RTL8192Usb_HW { - - PCIF = 0x009, // PCI Function Register 0x0009h~0x000bh -#define BB_GLOBAL_RESET_BIT 0x1 - BB_GLOBAL_RESET = 0x020, // BasebandGlobal Reset Register - BSSIDR = 0x02E, // BSSID Register - CMDR = 0x037, // Command register -#define CR_RST 0x10 -#define CR_RE 0x08 -#define CR_TE 0x04 -#define CR_MulRW 0x01 - SIFS = 0x03E, // SIFS register - TCR = 0x040, // Transmit Configuration Register - -#define TCR_MXDMA_2048 7 -#define TCR_LRL_OFFSET 0 -#define TCR_SRL_OFFSET 8 -#define TCR_MXDMA_OFFSET 21 -#define TCR_SAT BIT24 // Enable Rate depedent ack timeout timer - RCR = 0x044, // Receive Configuration Register -#define MAC_FILTER_MASK ((1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<5) | \ - (1<<12) | (1<<18) | (1<<19) | (1<<20) | (1<<21) | (1<<22) | (1<<23)) -#define RX_FIFO_THRESHOLD_MASK ((1<<13) | (1<<14) | (1<<15)) -#define RX_FIFO_THRESHOLD_SHIFT 13 -#define RX_FIFO_THRESHOLD_128 3 -#define RX_FIFO_THRESHOLD_256 4 -#define RX_FIFO_THRESHOLD_512 5 -#define RX_FIFO_THRESHOLD_1024 6 -#define RX_FIFO_THRESHOLD_NONE 7 -#define MAX_RX_DMA_MASK ((1<<8) | (1<<9) | (1<<10)) -#define RCR_MXDMA_OFFSET 8 -#define RCR_FIFO_OFFSET 13 -#define RCR_ONLYERLPKT BIT31 // Early Receiving based on Packet Size. -#define RCR_ENCS2 BIT30 // Enable Carrier Sense Detection Method 2 -#define RCR_ENCS1 BIT29 // Enable Carrier Sense Detection Method 1 -#define RCR_ENMBID BIT27 // Enable Multiple BssId. -#define RCR_ACKTXBW (BIT24|BIT25) // TXBW Setting of ACK frames -#define RCR_CBSSID BIT23 // Accept BSSID match packet -#define RCR_APWRMGT BIT22 // Accept power management packet -#define RCR_ADD3 BIT21 // Accept address 3 match packet -#define RCR_AMF BIT20 // Accept management type frame -#define RCR_ACF BIT19 // Accept control type frame -#define RCR_ADF BIT18 // Accept data type frame -#define RCR_RXFTH BIT13 // Rx FIFO Threshold -#define RCR_AICV BIT12 // Accept ICV error packet -#define RCR_ACRC32 BIT5 // Accept CRC32 error packet -#define RCR_AB BIT3 // Accept broadcast packet -#define RCR_AM BIT2 // Accept multicast packet -#define RCR_APM BIT1 // Accept physical match packet -#define RCR_AAP BIT0 // Accept all unicast packet - SLOT_TIME = 0x049, // Slot Time Register - ACK_TIMEOUT = 0x04c, // Ack Timeout Register - PIFS_TIME = 0x04d, // PIFS time - USTIME = 0x04e, // Microsecond Tuning Register, Sets the microsecond time unit used by MAC clock. - EDCAPARA_BE = 0x050, // EDCA Parameter of AC BE - EDCAPARA_BK = 0x054, // EDCA Parameter of AC BK - EDCAPARA_VO = 0x058, // EDCA Parameter of AC VO - EDCAPARA_VI = 0x05C, // EDCA Parameter of AC VI - RFPC = 0x05F, // Rx FIFO Packet Count - CWRR = 0x060, // Contention Window Report Register - BCN_TCFG = 0x062, // Beacon Time Configuration -#define BCN_TCFG_CW_SHIFT 8 -#define BCN_TCFG_IFS 0 - BCN_INTERVAL = 0x070, // Beacon Interval (TU) - ATIMWND = 0x072, // ATIM Window Size (TU) - BCN_DRV_EARLY_INT = 0x074, // Driver Early Interrupt Time (TU). Time to send interrupt to notify to change beacon content before TBTT - BCN_DMATIME = 0x076, // Beacon DMA and ATIM interrupt time (US). Indicates the time before TBTT to perform beacon queue DMA - BCN_ERR_THRESH = 0x078, // Beacon Error Threshold - RWCAM = 0x0A0, //IN 8190 Data Sheet is called CAMcmd - WCAMI = 0x0A4, // Software write CAM input content - RCAMO = 0x0A8, // Software read/write CAM config - SECR = 0x0B0, //Security Configuration Register -#define SCR_TxUseDK BIT0 //Force Tx Use Default Key -#define SCR_RxUseDK BIT1 //Force Rx Use Default Key -#define SCR_TxEncEnable BIT2 //Enable Tx Encryption -#define SCR_RxDecEnable BIT3 //Enable Rx Decryption -#define SCR_SKByA2 BIT4 //Search kEY BY A2 -#define SCR_NoSKMC BIT5 //No Key Search for Multicast -#define SCR_UseDK 0x01 -#define SCR_TxSecEnable 0x02 -#define SCR_RxSecEnable 0x04 - TPPoll = 0x0fd, // Transmit priority polling register - PSR = 0x0ff, // Page Select Register -#define CPU_CCK_LOOPBACK 0x00030000 -#define CPU_GEN_SYSTEM_RESET 0x00000001 -#define CPU_GEN_FIRMWARE_RESET 0x00000008 -#define CPU_GEN_BOOT_RDY 0x00000010 -#define CPU_GEN_FIRM_RDY 0x00000020 -#define CPU_GEN_PUT_CODE_OK 0x00000080 -#define CPU_GEN_BB_RST 0x00000100 -#define CPU_GEN_PWR_STB_CPU 0x00000004 -#define CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF // Set bit18,17,16 to 0. Set bit19 -#define CPU_GEN_NO_LOOPBACK_SET 0x00080000 // Set BIT19 to 1 - -//---------------------------------------------------------------------------- -// 8190 CPU General Register (offset 0x100, 4 byte) -//---------------------------------------------------------------------------- -#define CPU_CCK_LOOPBACK 0x00030000 -#define CPU_GEN_SYSTEM_RESET 0x00000001 -#define CPU_GEN_FIRMWARE_RESET 0x00000008 -#define CPU_GEN_BOOT_RDY 0x00000010 -#define CPU_GEN_FIRM_RDY 0x00000020 -#define CPU_GEN_PUT_CODE_OK 0x00000080 -#define CPU_GEN_BB_RST 0x00000100 -#define CPU_GEN_PWR_STB_CPU 0x00000004 -#define CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF // Set bit18,17,16 to 0. Set bit19 -#define CPU_GEN_NO_LOOPBACK_SET 0x00080000 // Set BIT19 to 1 - CPU_GEN = 0x100, // CPU Reset Register - LED1Cfg = 0x154,// LED1 Configuration Register - LED0Cfg = 0x155,// LED0 Configuration Register - - AcmAvg = 0x170, // ACM Average Period Register - AcmHwCtrl = 0x171, // ACM Hardware Control Register -//---------------------------------------------------------------------------- -//// -//// 8190 AcmHwCtrl bits (offset 0x171, 1 byte) -////---------------------------------------------------------------------------- -// -#define AcmHw_HwEn BIT0 -#define AcmHw_BeqEn BIT1 -#define AcmHw_ViqEn BIT2 -#define AcmHw_VoqEn BIT3 -#define AcmHw_BeqStatus BIT4 -#define AcmHw_ViqStatus BIT5 -#define AcmHw_VoqStatus BIT6 - - AcmFwCtrl = 0x172, // ACM Firmware Control Register - AES_11N_FIX = 0x173, - VOAdmTime = 0x174, // VO Queue Admitted Time Register - VIAdmTime = 0x178, // VI Queue Admitted Time Register - BEAdmTime = 0x17C, // BE Queue Admitted Time Register - RQPN1 = 0x180, // Reserved Queue Page Number , Vo Vi, Be, Bk - RQPN2 = 0x184, // Reserved Queue Page Number, HCCA, Cmd, Mgnt, High - RQPN3 = 0x188, // Reserved Queue Page Number, Bcn, Public, -// QPRR = 0x1E0, // Queue Page Report per TID - QPNR = 0x1D0, //0x1F0, // Queue Packet Number report per TID - BQDA = 0x200, // Beacon Queue Descriptor Address - HQDA = 0x204, // High Priority Queue Descriptor Address - CQDA = 0x208, // Command Queue Descriptor Address - MQDA = 0x20C, // Management Queue Descriptor Address - HCCAQDA = 0x210, // HCCA Queue Descriptor Address - VOQDA = 0x214, // VO Queue Descriptor Address - VIQDA = 0x218, // VI Queue Descriptor Address - BEQDA = 0x21C, // BE Queue Descriptor Address - BKQDA = 0x220, // BK Queue Descriptor Address - RCQDA = 0x224, // Receive command Queue Descriptor Address - RDQDA = 0x228, // Receive Queue Descriptor Start Address - - MAR0 = 0x240, // Multicast filter. - MAR4 = 0x244, - - CCX_PERIOD = 0x250, // CCX Measurement Period Register, in unit of TU. - CLM_RESULT = 0x251, // CCA Busy fraction register. - NHM_PERIOD = 0x252, // NHM Measurement Period register, in unit of TU. - - NHM_THRESHOLD0 = 0x253, // Noise Histogram Meashorement0. - NHM_THRESHOLD1 = 0x254, // Noise Histogram Meashorement1. - NHM_THRESHOLD2 = 0x255, // Noise Histogram Meashorement2. - NHM_THRESHOLD3 = 0x256, // Noise Histogram Meashorement3. - NHM_THRESHOLD4 = 0x257, // Noise Histogram Meashorement4. - NHM_THRESHOLD5 = 0x258, // Noise Histogram Meashorement5. - NHM_THRESHOLD6 = 0x259, // Noise Histogram Meashorement6 - - MCTRL = 0x25A, // Measurement Control - - NHM_RPI_COUNTER0 = 0x264, // Noise Histogram RPI counter0, the fraction of signal strength < NHM_THRESHOLD0. - NHM_RPI_COUNTER1 = 0x265, // Noise Histogram RPI counter1, the fraction of signal strength in (NHM_THRESHOLD0, NHM_THRESHOLD1]. - NHM_RPI_COUNTER2 = 0x266, // Noise Histogram RPI counter2, the fraction of signal strength in (NHM_THRESHOLD1, NHM_THRESHOLD2]. - NHM_RPI_COUNTER3 = 0x267, // Noise Histogram RPI counter3, the fraction of signal strength in (NHM_THRESHOLD2, NHM_THRESHOLD3]. - NHM_RPI_COUNTER4 = 0x268, // Noise Histogram RPI counter4, the fraction of signal strength in (NHM_THRESHOLD3, NHM_THRESHOLD4]. - NHM_RPI_COUNTER5 = 0x269, // Noise Histogram RPI counter5, the fraction of signal strength in (NHM_THRESHOLD4, NHM_THRESHOLD5]. - NHM_RPI_COUNTER6 = 0x26A, // Noise Histogram RPI counter6, the fraction of signal strength in (NHM_THRESHOLD5, NHM_THRESHOLD6]. - NHM_RPI_COUNTER7 = 0x26B, // Noise Histogram RPI counter7, the fraction of signal strength in (NHM_THRESHOLD6, NHM_THRESHOLD7]. -#define BW_OPMODE_11J BIT0 -#define BW_OPMODE_5G BIT1 -#define BW_OPMODE_20MHZ BIT2 - BW_OPMODE = 0x300, // Bandwidth operation mode - MSR = 0x303, // Media Status register -#define MSR_LINK_MASK ((1<<0)|(1<<1)) -#define MSR_LINK_MANAGED 2 -#define MSR_LINK_NONE 0 -#define MSR_LINK_SHIFT 0 -#define MSR_LINK_ADHOC 1 -#define MSR_LINK_MASTER 3 -#define MSR_LINK_ENEDCA (1<<4) - RETRY_LIMIT = 0x304, // Retry Limit [15:8]-short, [7:0]-long -#define RETRY_LIMIT_SHORT_SHIFT 8 -#define RETRY_LIMIT_LONG_SHIFT 0 - TSFR = 0x308, - RRSR = 0x310, // Response Rate Set -#define RRSR_RSC_OFFSET 21 -#define RRSR_SHORT_OFFSET 23 -#define RRSR_RSC_DUPLICATE 0x600000 -#define RRSR_RSC_LOWSUBCHNL 0x400000 -#define RRSR_RSC_UPSUBCHANL 0x200000 -#define RRSR_SHORT 0x800000 -#define RRSR_1M BIT0 -#define RRSR_2M BIT1 -#define RRSR_5_5M BIT2 -#define RRSR_11M BIT3 -#define RRSR_6M BIT4 -#define RRSR_9M BIT5 -#define RRSR_12M BIT6 -#define RRSR_18M BIT7 -#define RRSR_24M BIT8 -#define RRSR_36M BIT9 -#define RRSR_48M BIT10 -#define RRSR_54M BIT11 -#define RRSR_MCS0 BIT12 -#define RRSR_MCS1 BIT13 -#define RRSR_MCS2 BIT14 -#define RRSR_MCS3 BIT15 -#define RRSR_MCS4 BIT16 -#define RRSR_MCS5 BIT17 -#define RRSR_MCS6 BIT18 -#define RRSR_MCS7 BIT19 -#define BRSR_AckShortPmb BIT23 // CCK ACK: use Short Preamble or not. - RATR0 = 0x320, // Rate Adaptive Table register1 - UFWP = 0x318, - DRIVER_RSSI = 0x32c, // Driver tell Firmware current RSSI -//---------------------------------------------------------------------------- -// 8190 Rate Adaptive Table Register (offset 0x320, 4 byte) -//---------------------------------------------------------------------------- -//CCK -#define RATR_1M 0x00000001 -#define RATR_2M 0x00000002 -#define RATR_55M 0x00000004 -#define RATR_11M 0x00000008 -//OFDM -#define RATR_6M 0x00000010 -#define RATR_9M 0x00000020 -#define RATR_12M 0x00000040 -#define RATR_18M 0x00000080 -#define RATR_24M 0x00000100 -#define RATR_36M 0x00000200 -#define RATR_48M 0x00000400 -#define RATR_54M 0x00000800 -//MCS 1 Spatial Stream -#define RATR_MCS0 0x00001000 -#define RATR_MCS1 0x00002000 -#define RATR_MCS2 0x00004000 -#define RATR_MCS3 0x00008000 -#define RATR_MCS4 0x00010000 -#define RATR_MCS5 0x00020000 -#define RATR_MCS6 0x00040000 -#define RATR_MCS7 0x00080000 -//MCS 2 Spatial Stream -#define RATR_MCS8 0x00100000 -#define RATR_MCS9 0x00200000 -#define RATR_MCS10 0x00400000 -#define RATR_MCS11 0x00800000 -#define RATR_MCS12 0x01000000 -#define RATR_MCS13 0x02000000 -#define RATR_MCS14 0x04000000 -#define RATR_MCS15 0x08000000 -// ALL CCK Rate -#define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M -#define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M\ - |RATR_36M|RATR_48M|RATR_54M -#define RATE_ALL_OFDM_1SS RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 | \ - RATR_MCS4|RATR_MCS5|RATR_MCS6|RATR_MCS7 -#define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9 |RATR_MCS10|RATR_MCS11| \ - RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15 - - MCS_TXAGC = 0x340, // MCS AGC - CCK_TXAGC = 0x348, // CCK AGC -// ISR = 0x350, // Interrupt Status Register -// IMR = 0x354, // Interrupt Mask Register -// IMR_POLL = 0x360, - MacBlkCtrl = 0x403, // Mac block on/off control register - - EPROM_CMD = 0xfe58, -#define Cmd9346CR_9356SEL (1<<4) -#define EPROM_CMD_RESERVED_MASK (1<<5) -#define EPROM_CMD_OPERATING_MODE_SHIFT 6 -#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6)) -#define EPROM_CMD_CONFIG 0x3 -#define EPROM_CMD_NORMAL 0 -#define EPROM_CMD_LOAD 1 -#define EPROM_CMD_PROGRAM 2 -#define EPROM_CS_SHIFT 3 -#define EPROM_CK_SHIFT 2 -#define EPROM_W_SHIFT 1 -#define EPROM_R_SHIFT 0 - MAC0 = 0x000, - MAC1 = 0x001, - MAC2 = 0x002, - MAC3 = 0x003, - MAC4 = 0x004, - MAC5 = 0x005, - -#if 0 -/* 0x0006 - 0x0007 - reserved */ - RXFIFOCOUNT = 0x010, - TXFIFOCOUNT = 0x012, - BQREQ = 0x013, -/* 0x0010 - 0x0017 - reserved */ - TSFTR = 0x018, - TLPDA = 0x020, - TNPDA = 0x024, - THPDA = 0x028, - BSSID = 0x02E, - RESP_RATE = 0x034, - CMD = 0x037, -#define CMD_RST_SHIFT 4 -#define CMD_RESERVED_MASK ((1<<1) | (1<<5) | (1<<6) | (1<<7)) -#define CMD_RX_ENABLE_SHIFT 3 -#define CMD_TX_ENABLE_SHIFT 2 -#define CR_RST ((1<< 4)) -#define CR_RE ((1<< 3)) -#define CR_TE ((1<< 2)) -#define CR_MulRW ((1<< 0)) - - INTA_MASK = 0x03c, - INTA = 0x03e, -#define INTA_TXOVERFLOW (1<<15) -#define INTA_TIMEOUT (1<<14) -#define INTA_BEACONTIMEOUT (1<<13) -#define INTA_ATIM (1<<12) -#define INTA_BEACONDESCERR (1<<11) -#define INTA_BEACONDESCOK (1<<10) -#define INTA_HIPRIORITYDESCERR (1<<9) -#define INTA_HIPRIORITYDESCOK (1<<8) -#define INTA_NORMPRIORITYDESCERR (1<<7) -#define INTA_NORMPRIORITYDESCOK (1<<6) -#define INTA_RXOVERFLOW (1<<5) -#define INTA_RXDESCERR (1<<4) -#define INTA_LOWPRIORITYDESCERR (1<<3) -#define INTA_LOWPRIORITYDESCOK (1<<2) -#define INTA_RXCRCERR (1<<1) -#define INTA_RXOK (1) - TX_CONF = 0x040, -#define TX_CONF_HEADER_AUTOICREMENT_SHIFT 30 -#define TX_LOOPBACK_SHIFT 17 -#define TX_LOOPBACK_MAC 1 -#define TX_LOOPBACK_BASEBAND 2 -#define TX_LOOPBACK_NONE 0 -#define TX_LOOPBACK_CONTINUE 3 -#define TX_LOOPBACK_MASK ((1<<17)|(1<<18)) -#define TX_LRLRETRY_SHIFT 0 -#define TX_SRLRETRY_SHIFT 8 -#define TX_NOICV_SHIFT 19 -#define TX_NOCRC_SHIFT 16 -#define TCR_DurProcMode ((1<<30)) -#define TCR_DISReqQsize ((1<<28)) -#define TCR_HWVERID_MASK ((1<<27)|(1<<26)|(1<<25)) -#define TCR_HWVERID_SHIFT 25 -#define TCR_SWPLCPLEN ((1<<24)) -#define TCR_PLCP_LEN TCR_SAT // rtl8180 -#define TCR_MXDMA_MASK ((1<<23)|(1<<22)|(1<<21)) -#define TCR_MXDMA_1024 6 -#define TCR_MXDMA_2048 7 -#define TCR_MXDMA_SHIFT 21 -#define TCR_DISCW ((1<<20)) -#define TCR_ICV ((1<<19)) -#define TCR_LBK ((1<<18)|(1<<17)) -#define TCR_LBK1 ((1<<18)) -#define TCR_LBK0 ((1<<17)) -#define TCR_CRC ((1<<16)) -#define TCR_SRL_MASK ((1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(1<<10)|(1<<9)|(1<<8)) -#define TCR_LRL_MASK ((1<<0)|(1<<1)|(1<<2)|(1<<3)|(1<<4)|(1<<5)|(1<<6)|(1<<7)) -#define TCR_PROBE_NOTIMESTAMP_SHIFT 29 //rtl8185 - RX_CONF = 0x044, -#define MAC_FILTER_MASK ((1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<5) | \ -(1<<12) | (1<<18) | (1<<19) | (1<<20) | (1<<21) | (1<<22) | (1<<23)) -#define RX_CHECK_BSSID_SHIFT 23 -#define ACCEPT_PWR_FRAME_SHIFT 22 -#define ACCEPT_MNG_FRAME_SHIFT 20 -#define ACCEPT_CTL_FRAME_SHIFT 19 -#define ACCEPT_DATA_FRAME_SHIFT 18 -#define ACCEPT_ICVERR_FRAME_SHIFT 12 -#define ACCEPT_CRCERR_FRAME_SHIFT 5 -#define ACCEPT_BCAST_FRAME_SHIFT 3 -#define ACCEPT_MCAST_FRAME_SHIFT 2 -#define ACCEPT_ALLMAC_FRAME_SHIFT 0 -#define ACCEPT_NICMAC_FRAME_SHIFT 1 -#define RX_FIFO_THRESHOLD_MASK ((1<<13) | (1<<14) | (1<<15)) -#define RX_FIFO_THRESHOLD_SHIFT 13 -#define RX_FIFO_THRESHOLD_128 3 -#define RX_FIFO_THRESHOLD_256 4 -#define RX_FIFO_THRESHOLD_512 5 -#define RX_FIFO_THRESHOLD_1024 6 -#define RX_FIFO_THRESHOLD_NONE 7 -#define RX_AUTORESETPHY_SHIFT 28 -#define MAX_RX_DMA_MASK ((1<<8) | (1<<9) | (1<<10)) -#define MAX_RX_DMA_2048 7 -#define MAX_RX_DMA_1024 6 -#define MAX_RX_DMA_SHIFT 10 -#define RCR_ONLYERLPKT ((1<<31)) -#define RCR_CS_SHIFT 29 -#define RCR_CS_MASK ((1<<30) | (1<<29)) -#define RCR_ENMARP ((1<<28)) -#define RCR_CBSSID ((1<<23)) -#define RCR_APWRMGT ((1<<22)) -#define RCR_ADD3 ((1<<21)) -#define RCR_AMF ((1<<20)) -#define RCR_ACF ((1<<19)) -#define RCR_ADF ((1<<18)) -#define RCR_RXFTH ((1<<15)|(1<<14)|(1<<13)) -#define RCR_RXFTH2 ((1<<15)) -#define RCR_RXFTH1 ((1<<14)) -#define RCR_RXFTH0 ((1<<13)) -#define RCR_AICV ((1<<12)) -#define RCR_MXDMA ((1<<10)|(1<< 9)|(1<< 8)) -#define RCR_MXDMA2 ((1<<10)) -#define RCR_MXDMA1 ((1<< 9)) -#define RCR_MXDMA0 ((1<< 8)) -#define RCR_9356SEL ((1<< 6)) -#define RCR_ACRC32 ((1<< 5)) -#define RCR_AB ((1<< 3)) -#define RCR_AM ((1<< 2)) -#define RCR_APM ((1<< 1)) -#define RCR_AAP ((1<< 0)) - INT_TIMEOUT = 0x048, - TX_BEACON_RING_ADDR = 0x04c, - EPROM_CMD = 0x58, -#define EPROM_CMD_RESERVED_MASK ((1<<5)|(1<<4)) -#define EPROM_CMD_OPERATING_MODE_SHIFT 6 -#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6)) -#define EPROM_CMD_CONFIG 0x3 -#define EPROM_CMD_NORMAL 0 -#define EPROM_CMD_LOAD 1 -#define EPROM_CMD_PROGRAM 2 -#define EPROM_CS_SHIFT 3 -#define EPROM_CK_SHIFT 2 -#define EPROM_W_SHIFT 1 -#define EPROM_R_SHIFT 0 - CONFIG0 = 0x051, -#define CONFIG0_WEP104 ((1<<6)) -#define CONFIG0_LEDGPO_En ((1<<4)) -#define CONFIG0_Aux_Status ((1<<3)) -#define CONFIG0_GL ((1<<1)|(1<<0)) -#define CONFIG0_GL1 ((1<<1)) -#define CONFIG0_GL0 ((1<<0)) - CONFIG1 = 0x052, -#define CONFIG1_LEDS ((1<<7)|(1<<6)) -#define CONFIG1_LEDS1 ((1<<7)) -#define CONFIG1_LEDS0 ((1<<6)) -#define CONFIG1_LWACT ((1<<4)) -#define CONFIG1_MEMMAP ((1<<3)) -#define CONFIG1_IOMAP ((1<<2)) -#define CONFIG1_VPD ((1<<1)) -#define CONFIG1_PMEn ((1<<0)) - CONFIG2 = 0x053, -#define CONFIG2_LCK ((1<<7)) -#define CONFIG2_ANT ((1<<6)) -#define CONFIG2_DPS ((1<<3)) -#define CONFIG2_PAPE_sign ((1<<2)) -#define CONFIG2_PAPE_time ((1<<1)|(1<<0)) -#define CONFIG2_PAPE_time1 ((1<<1)) -#define CONFIG2_PAPE_time0 ((1<<0)) - ANA_PARAM = 0x054, - CONFIG3 = 0x059, -#define CONFIG3_GNTSel ((1<<7)) -#define CONFIG3_PARM_En ((1<<6)) -#define CONFIG3_Magic ((1<<5)) -#define CONFIG3_CardB_En ((1<<3)) -#define CONFIG3_CLKRUN_En ((1<<2)) -#define CONFIG3_FuncRegEn ((1<<1)) -#define CONFIG3_FBtbEn ((1<<0)) -#define CONFIG3_CLKRUN_SHIFT 2 -#define CONFIG3_ANAPARAM_W_SHIFT 6 - CONFIG4 = 0x05a, -#define CONFIG4_VCOPDN ((1<<7)) -#define CONFIG4_PWROFF ((1<<6)) -#define CONFIG4_PWRMGT ((1<<5)) -#define CONFIG4_LWPME ((1<<4)) -#define CONFIG4_LWPTN ((1<<2)) -#define CONFIG4_RFTYPE ((1<<1)|(1<<0)) -#define CONFIG4_RFTYPE1 ((1<<1)) -#define CONFIG4_RFTYPE0 ((1<<0)) - TESTR = 0x05b, -#define TFPC_AC 0x05C - -#define SCR 0x05F - PGSELECT = 0x05e, -#define PGSELECT_PG_SHIFT 0 - SECURITY = 0x05f, -#define SECURITY_WEP_TX_ENABLE_SHIFT 1 -#define SECURITY_WEP_RX_ENABLE_SHIFT 0 -#define SECURITY_ENCRYP_104 1 -#define SECURITY_ENCRYP_SHIFT 4 -#define SECURITY_ENCRYP_MASK ((1<<4)|(1<<5)) - ANA_PARAM2 = 0x060, - BEACON_INTERVAL = 0x070, -#define BEACON_INTERVAL_MASK ((1<<0)|(1<<1)|(1<<2)|(1<<3)|(1<<4)|(1<<5)| \ -(1<<6)|(1<<7)|(1<<8)|(1<<9)) - ATIM_WND = 0x072, -#define ATIM_WND_MASK (0x01FF) - BCN_INTR_ITV = 0x074, -#define BCN_INTR_ITV_MASK (0x01FF) - ATIM_INTR_ITV = 0x076, -#define ATIM_INTR_ITV_MASK (0x01FF) - AckTimeOutReg = 0x079, //ACK timeout register, in unit of 4 us. - PHY_ADR = 0x07c, - PHY_READ = 0x07e, - RFPinsOutput = 0x080, - RFPinsEnable = 0x082, - -//Page 0 - RFPinsSelect = 0x084, -#define SW_CONTROL_GPIO 0x400 - RFPinsInput = 0x086, - RF_PARA = 0x088, - RF_TIMING = 0x08c, - GP_ENABLE = 0x090, - GPIO = 0x091, - TX_AGC_CTL = 0x09c, -#define TX_AGC_CTL_PER_PACKET_TXAGC 0x01 -#define TX_AGC_CTL_PERPACKET_GAIN_SHIFT 0 -#define TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT 1 -#define TX_AGC_CTL_FEEDBACK_ANT 2 -#define TXAGC_CTL_PER_PACKET_ANT_SEL 0x02 - OFDM_TXAGC = 0x09e, - ANTSEL = 0x09f, - WPA_CONFIG = 0x0b0, - SIFS = 0x0b4, - DIFS = 0x0b5, - SLOT = 0x0b6, - CW_CONF = 0x0bc, -#define CW_CONF_PERPACKET_RETRY_LIMIT 0x02 -#define CW_CONF_PERPACKET_CW 0x01 -#define CW_CONF_PERPACKET_RETRY_SHIFT 1 -#define CW_CONF_PERPACKET_CW_SHIFT 0 - CW_VAL = 0x0bd, - RATE_FALLBACK = 0x0be, -#define MAX_RESP_RATE_SHIFT 4 -#define MIN_RESP_RATE_SHIFT 0 -#define RATE_FALLBACK_CTL_ENABLE 0x80 -#define RATE_FALLBACK_CTL_AUTO_STEP0 0x00 - ACM_CONTROL = 0x0BF, // ACM Control Registe -//---------------------------------------------------------------------------- -// 8187B ACM_CONTROL bits (Offset 0xBF, 1 Byte) -//---------------------------------------------------------------------------- -#define VOQ_ACM_EN (0x01 << 7) //BIT7 -#define VIQ_ACM_EN (0x01 << 6) //BIT6 -#define BEQ_ACM_EN (0x01 << 5) //BIT5 -#define ACM_HW_EN (0x01 << 4) //BIT4 -#define TXOPSEL (0x01 << 3) //BIT3 -#define VOQ_ACM_CTL (0x01 << 2) //BIT2 // Set to 1 when AC_VO used time reaches or exceeds the admitted time -#define VIQ_ACM_CTL (0x01 << 1) //BIT1 // Set to 1 when AC_VI used time reaches or exceeds the admitted time -#define BEQ_ACM_CTL (0x01 << 0) //BIT0 // Set to 1 when AC_BE used time reaches or exceeds the admitted time - CONFIG5 = 0x0D8, -#define CONFIG5_TX_FIFO_OK ((1<<7)) -#define CONFIG5_RX_FIFO_OK ((1<<6)) -#define CONFIG5_CALON ((1<<5)) -#define CONFIG5_EACPI ((1<<2)) -#define CONFIG5_LANWake ((1<<1)) -#define CONFIG5_PME_STS ((1<<0)) - TX_DMA_POLLING = 0x0d9, -#define TX_DMA_POLLING_BEACON_SHIFT 7 -#define TX_DMA_POLLING_HIPRIORITY_SHIFT 6 -#define TX_DMA_POLLING_NORMPRIORITY_SHIFT 5 -#define TX_DMA_POLLING_LOWPRIORITY_SHIFT 4 -#define TX_DMA_STOP_BEACON_SHIFT 3 -#define TX_DMA_STOP_HIPRIORITY_SHIFT 2 -#define TX_DMA_STOP_NORMPRIORITY_SHIFT 1 -#define TX_DMA_STOP_LOWPRIORITY_SHIFT 0 - CWR = 0x0DC, - RetryCTR = 0x0DE, - INT_MIG = 0x0E2, // Interrupt Migration (0xE2 ~ 0xE3) - TID_AC_MAP = 0x0E8, // TID to AC Mapping Register - ANA_PARAM3 = 0x0EE, - - -//page 1 - Wakeup0 = 0x084, - Wakeup1 = 0x08C, - Wakeup2LD = 0x094, - Wakeup2HD = 0x09C, - Wakeup3LD = 0x0A4, - Wakeup3HD = 0x0AC, - Wakeup4LD = 0x0B4, - Wakeup4HD = 0x0BC, - CRC0 = 0x0C4, - CRC1 = 0x0C6, - CRC2 = 0x0C8, - CRC3 = 0x0CA, - CRC4 = 0x0CC, -/* 0x00CE - 0x00D3 - reserved */ - - RFSW_CTRL = 0x272, // 0x272-0x273. - -//Reg Diff between rtl8187 and rtl8187B -/**************************************************************************/ - BRSR_8187 = 0x02C, - BRSR_8187B = 0x034, -#define BRSR_BPLCP ((1<< 8)) -#define BRSR_MBR ((1<< 1)|(1<< 0)) -#define BRSR_MBR_8185 ((1<< 11)|(1<< 10)|(1<< 9)|(1<< 8)|(1<< 7)|(1<< 6)|(1<< 5)|(1<< 4)|(1<< 3)|(1<< 2)|(1<< 1)|(1<< 0)) -#define BRSR_MBR0 ((1<< 0)) -#define BRSR_MBR1 ((1<< 1)) - -/**************************************************************************/ - EIFS_8187 = 0x035, - EIFS_8187B = 0x02D, - -/**************************************************************************/ - FER = 0x0F0, - FEMR = 0x0F4, - FPSR = 0x0F8, - FFER = 0x0FC, - - AC_VO_PARAM = 0x0F0, // AC_VO Parameters Record - AC_VI_PARAM = 0x0F4, // AC_VI Parameters Record - AC_BE_PARAM = 0x0F8, // AC_BE Parameters Record - AC_BK_PARAM = 0x0FC, // AC_BK Parameters Record - TALLY_SEL = 0x0fc, -//---------------------------------------------------------------------------- -// 8187B AC_XX_PARAM bits -//---------------------------------------------------------------------------- -#define AC_PARAM_TXOP_LIMIT_OFFSET 16 -#define AC_PARAM_ECW_MAX_OFFSET 12 -#define AC_PARAM_ECW_MIN_OFFSET 8 -#define AC_PARAM_AIFS_OFFSET 0 - -#endif -}; -//---------------------------------------------------------------------------- -// 818xB AnaParm & AnaParm2 Register -//---------------------------------------------------------------------------- -//#define ANAPARM_ASIC_ON 0x45090658 -//#define ANAPARM2_ASIC_ON 0x727f3f52 -#define GPI 0x108 -#define GPO 0x109 -#define GPE 0x10a -#endif diff --git a/drivers/staging/rtl8192su/r819xU_firmware.c b/drivers/staging/rtl8192su/r819xU_firmware.c deleted file mode 100644 index 6a10bc11d97a..000000000000 --- a/drivers/staging/rtl8192su/r819xU_firmware.c +++ /dev/null @@ -1,697 +0,0 @@ -/************************************************************************************************** - * Procedure: Init boot code/firmware code/data session - * - * Description: This routine will intialize firmware. If any error occurs during the initialization - * process, the routine shall terminate immediately and return fail. - * NIC driver should call NdisOpenFile only from MiniportInitialize. - * - * Arguments: The pointer of the adapter - - * Returns: - * NDIS_STATUS_FAILURE - the following initialization process should be terminated - * NDIS_STATUS_SUCCESS - if firmware initialization process success -**************************************************************************************************/ -#include "r8192U.h" -#include "r8192U_hw.h" -#include "r819xU_firmware_img.h" -#include "r819xU_firmware.h" -#include <linux/firmware.h> - -void firmware_init_param(struct net_device *dev) -{ - struct r8192_priv *priv = ieee80211_priv(dev); - rt_firmware *pfirmware = priv->pFirmware; - - pfirmware->cmdpacket_frag_thresold = GET_COMMAND_PACKET_FRAG_THRESHOLD(MAX_TRANSMIT_BUFFER_SIZE); -} - -/* - * segment the img and use the ptr and length to remember info on each segment - * - */ -bool fw_download_code(struct net_device *dev, u8 *code_virtual_address, u32 buffer_len) -{ - struct r8192_priv *priv = ieee80211_priv(dev); - bool rt_status = true; - u16 frag_threshold; - u16 frag_length, frag_offset = 0; - //u16 total_size; - int i; - - rt_firmware *pfirmware = priv->pFirmware; - struct sk_buff *skb; - unsigned char *seg_ptr; - cb_desc *tcb_desc; - u8 bLastIniPkt; - - firmware_init_param(dev); - //Fragmentation might be required - frag_threshold = pfirmware->cmdpacket_frag_thresold; - do { - if((buffer_len - frag_offset) > frag_threshold) { - frag_length = frag_threshold ; - bLastIniPkt = 0; - - } else { - frag_length = buffer_len - frag_offset; - bLastIniPkt = 1; - - } - - /* Allocate skb buffer to contain firmware info and tx descriptor info - * add 4 to avoid packet appending overflow. - * */ - #ifdef RTL8192U - skb = dev_alloc_skb(USB_HWDESC_HEADER_LEN + frag_length + 4); - #else - skb = dev_alloc_skb(frag_length + 4); - #endif - memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev)); - tcb_desc = (cb_desc*)(skb->cb + MAX_DEV_ADDR_SIZE); - tcb_desc->queue_index = TXCMD_QUEUE; - tcb_desc->bCmdOrInit = DESC_PACKET_TYPE_INIT; - tcb_desc->bLastIniPkt = bLastIniPkt; - - #ifdef RTL8192U - skb_reserve(skb, USB_HWDESC_HEADER_LEN); - #endif - seg_ptr = skb->data; - /* - * Transform from little endian to big endian - * and pending zero - */ - for(i=0 ; i < frag_length; i+=4) { - *seg_ptr++ = ((i+0)<frag_length)?code_virtual_address[i+3]:0; - *seg_ptr++ = ((i+1)<frag_length)?code_virtual_address[i+2]:0; - *seg_ptr++ = ((i+2)<frag_length)?code_virtual_address[i+1]:0; - *seg_ptr++ = ((i+3)<frag_length)?code_virtual_address[i+0]:0; - } - tcb_desc->txbuf_size= (u16)i; - skb_put(skb, i); - - if(!priv->ieee80211->check_nic_enough_desc(dev,tcb_desc->queue_index)|| - (!skb_queue_empty(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index]))||\ - (priv->ieee80211->queue_stop) ) { - RT_TRACE(COMP_FIRMWARE,"=====================================================> tx full!\n"); - skb_queue_tail(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index], skb); - } else { - priv->ieee80211->softmac_hard_start_xmit(skb,dev); - } - - code_virtual_address += frag_length; - frag_offset += frag_length; - - }while(frag_offset < buffer_len); - - return rt_status; - -#if 0 -cmdsend_downloadcode_fail: - rt_status = false; - RT_TRACE(COMP_ERR, "CmdSendDownloadCode fail !!\n"); - return rt_status; -#endif -} - -bool -fwSendNullPacket( - struct net_device *dev, - u32 Length -) -{ - bool rtStatus = true; - struct r8192_priv *priv = ieee80211_priv(dev); - struct sk_buff *skb; - cb_desc *tcb_desc; - unsigned char *ptr_buf; - bool bLastInitPacket = false; - - //PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); - - //Get TCB and local buffer from common pool. (It is shared by CmdQ, MgntQ, and USB coalesce DataQ) - skb = dev_alloc_skb(Length+ 4); - memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev)); - tcb_desc = (cb_desc*)(skb->cb + MAX_DEV_ADDR_SIZE); - tcb_desc->queue_index = TXCMD_QUEUE; - tcb_desc->bCmdOrInit = DESC_PACKET_TYPE_INIT; - tcb_desc->bLastIniPkt = bLastInitPacket; - ptr_buf = skb_put(skb, Length); - memset(ptr_buf,0,Length); - tcb_desc->txbuf_size= (u16)Length; - - if(!priv->ieee80211->check_nic_enough_desc(dev,tcb_desc->queue_index)|| - (!skb_queue_empty(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index]))||\ - (priv->ieee80211->queue_stop) ) { - RT_TRACE(COMP_FIRMWARE,"===================NULL packet==================================> tx full!\n"); - skb_queue_tail(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index], skb); - } else { - priv->ieee80211->softmac_hard_start_xmit(skb,dev); - } - - //PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); - return rtStatus; -} - -#if 0 -/* - * Procedure : Download code into IMEM or DMEM - * Description: This routine will intialize firmware. If any error occurs during the initialization - * process, the routine shall terminate immediately and return fail. - * The routine copy virtual address get from opening of file into shared memory - * allocated during initialization. If code size larger than a conitneous shared - * memory may contain, the code should be divided into several section. - * !!!NOTES This finction should only be called during MPInitialization because - * A NIC driver should call NdisOpenFile only from MiniportInitialize. - * Arguments : The pointer of the adapter - * Code address (Virtual address, should fill descriptor with physical address) - * Code size - * Returns : - * RT_STATUS_FAILURE - the following initialization process should be terminated - * RT_STATUS_SUCCESS - if firmware initialization process success - */ -bool fwsend_download_code(struct net_device *dev) -{ - struct r8192_priv *priv = ieee80211_priv(dev); - rt_firmware *pfirmware = (rt_firmware*)(&priv->firmware); - - bool rt_status = true; - u16 length = 0; - u16 offset = 0; - u16 frag_threhold; - bool last_init_packet = false; - u32 check_txcmdwait_queueemptytime = 100000; - u16 cmd_buf_len; - u8 *ptr_cmd_buf; - - /* reset to 0 for first segment of img download */ - pfirmware->firmware_seg_index = 1; - - if(pfirmware->firmware_seg_index == pfirmware->firmware_seg_maxnum) { - last_init_packet = 1; - } - - cmd_buf_len = pfirmware->firmware_seg_container[pfirmware->firmware_seg_index-1].seg_size; - ptr_cmd_buf = pfirmware->firmware_seg_container[pfirmware->firmware_seg_index-1].seg_ptr; - rtl819xU_tx_cmd(dev, ptr_cmd_buf, cmd_buf_len, last_init_packet, DESC_PACKET_TYPE_INIT); - - rt_status = true; - return rt_status; -} -#endif - -//----------------------------------------------------------------------------- -// Procedure: Check whether main code is download OK. If OK, turn on CPU -// -// Description: CPU register locates in different page against general register. -// Switch to CPU register in the begin and switch back before return -// -// -// Arguments: The pointer of the adapter -// -// Returns: -// NDIS_STATUS_FAILURE - the following initialization process should be terminated -// NDIS_STATUS_SUCCESS - if firmware initialization process success -//----------------------------------------------------------------------------- -bool CPUcheck_maincodeok_turnonCPU(struct net_device *dev) -{ - struct r8192_priv *priv = ieee80211_priv(dev); - bool rt_status = true; - int check_putcodeOK_time = 200000, check_bootOk_time = 200000; - u32 CPU_status = 0; - - /* Check whether put code OK */ - do { - CPU_status = read_nic_dword(dev, CPU_GEN); - - if((CPU_status&CPU_GEN_PUT_CODE_OK) || (priv->usb_error==true)) - break; - - }while(check_putcodeOK_time--); - - if(!(CPU_status&CPU_GEN_PUT_CODE_OK)) { - RT_TRACE(COMP_ERR, "Download Firmware: Put code fail!\n"); - goto CPUCheckMainCodeOKAndTurnOnCPU_Fail; - } else { - RT_TRACE(COMP_FIRMWARE, "Download Firmware: Put code ok!\n"); - } - - /* Turn On CPU */ - CPU_status = read_nic_dword(dev, CPU_GEN); - write_nic_byte(dev, CPU_GEN, (u8)((CPU_status|CPU_GEN_PWR_STB_CPU)&0xff)); - mdelay(1000); - - /* Check whether CPU boot OK */ - do { - CPU_status = read_nic_dword(dev, CPU_GEN); - - if((CPU_status&CPU_GEN_BOOT_RDY)||(priv->usb_error == true)) - break; - }while(check_bootOk_time--); - - if(!(CPU_status&CPU_GEN_BOOT_RDY)) { - goto CPUCheckMainCodeOKAndTurnOnCPU_Fail; - } else { - RT_TRACE(COMP_FIRMWARE, "Download Firmware: Boot ready!\n"); - } - - return rt_status; - -CPUCheckMainCodeOKAndTurnOnCPU_Fail: - RT_TRACE(COMP_ERR, "ERR in %s()\n", __FUNCTION__); - rt_status = FALSE; - return rt_status; -} - -bool CPUcheck_firmware_ready(struct net_device *dev) -{ - struct r8192_priv *priv = ieee80211_priv(dev); - bool rt_status = true; - int check_time = 200000; - u32 CPU_status = 0; - - /* Check Firmware Ready */ - do { - CPU_status = read_nic_dword(dev, CPU_GEN); - - if((CPU_status&CPU_GEN_FIRM_RDY)||(priv->usb_error == true)) - break; - - }while(check_time--); - - if(!(CPU_status&CPU_GEN_FIRM_RDY)) - goto CPUCheckFirmwareReady_Fail; - else - RT_TRACE(COMP_FIRMWARE, "Download Firmware: Firmware ready!\n"); - - return rt_status; - -CPUCheckFirmwareReady_Fail: - RT_TRACE(COMP_ERR, "ERR in %s()\n", __FUNCTION__); - rt_status = false; - return rt_status; - -} - -bool init_firmware(struct net_device *dev) -{ - struct r8192_priv *priv = ieee80211_priv(dev); - bool rt_status = TRUE; - - u8 *firmware_img_buf[3] = { &rtl8190_fwboot_array[0], - &rtl8190_fwmain_array[0], - &rtl8190_fwdata_array[0]}; - - u32 firmware_img_len[3] = { sizeof(rtl8190_fwboot_array), - sizeof(rtl8190_fwmain_array), - sizeof(rtl8190_fwdata_array)}; - u32 file_length = 0; - u8 *mapped_file = NULL; - u32 init_step = 0; - opt_rst_type_e rst_opt = OPT_SYSTEM_RESET; - firmware_init_step_e starting_state = FW_INIT_STEP0_BOOT; - - rt_firmware *pfirmware = priv->pFirmware; - const struct firmware *fw_entry; - const char *fw_name[3] = { "RTL8192U/boot.img", - "RTL8192U/main.img", - "RTL8192U/data.img"}; - int rc; - - RT_TRACE(COMP_FIRMWARE, " PlatformInitFirmware()==>\n"); - - if (pfirmware->firmware_status == FW_STATUS_0_INIT ) { - /* it is called by reset */ - rst_opt = OPT_SYSTEM_RESET; - starting_state = FW_INIT_STEP0_BOOT; - // TODO: system reset - - }else if(pfirmware->firmware_status == FW_STATUS_5_READY) { - /* it is called by Initialize */ - rst_opt = OPT_FIRMWARE_RESET; - starting_state = FW_INIT_STEP2_DATA; - }else { - RT_TRACE(COMP_FIRMWARE, "PlatformInitFirmware: undefined firmware state\n"); - } - - /* - * Download boot, main, and data image for System reset. - * Download data image for firmware reseta - */ - priv->firmware_source = FW_SOURCE_IMG_FILE; - - for(init_step = starting_state; init_step <= FW_INIT_STEP2_DATA; init_step++) { - /* - * Open Image file, and map file to contineous memory if open file success. - * or read image file from array. Default load from IMG file - */ - if(rst_opt == OPT_SYSTEM_RESET) { - switch(priv->firmware_source) { - case FW_SOURCE_IMG_FILE: - if(pfirmware->firmware_buf_size[init_step] == 0) { - rc = request_firmware(&fw_entry, fw_name[init_step],&priv->udev->dev); - if(rc < 0 ) { - RT_TRACE(COMP_ERR, "request firmware fail!\n"); - goto download_firmware_fail; - } - - if(fw_entry->size > sizeof(pfirmware->firmware_buf[init_step])) { - //RT_TRACE(COMP_ERR, "img file size exceed the container buffer fail!\n"); - RT_TRACE(COMP_FIRMWARE, "img file size exceed the container buffer fail!, entry_size = %d, buf_size = %d\n",fw_entry->size,sizeof(pfirmware->firmware_buf[init_step])); - - goto download_firmware_fail; - } - - if(init_step != FW_INIT_STEP1_MAIN) { - memcpy(pfirmware->firmware_buf[init_step],fw_entry->data,fw_entry->size); - pfirmware->firmware_buf_size[init_step] = fw_entry->size; - } else { -#ifdef RTL8190P - memcpy(pfirmware->firmware_buf[init_step],fw_entry->data,fw_entry->size); - pfirmware->firmware_buf_size[init_step] = fw_entry->size; -#else - memset(pfirmware->firmware_buf[init_step],0,128); - memcpy(&pfirmware->firmware_buf[init_step][128],fw_entry->data,fw_entry->size); - mapped_file = pfirmware->firmware_buf[init_step]; - pfirmware->firmware_buf_size[init_step] = fw_entry->size+128; -#endif - } - //pfirmware->firmware_buf_size = file_length; - - if(rst_opt == OPT_SYSTEM_RESET) { - release_firmware(fw_entry); - } - } - mapped_file = pfirmware->firmware_buf[init_step]; - file_length = pfirmware->firmware_buf_size[init_step]; - break; - - case FW_SOURCE_HEADER_FILE: - mapped_file = firmware_img_buf[init_step]; - file_length = firmware_img_len[init_step]; - if(init_step == FW_INIT_STEP2_DATA) { - memcpy(pfirmware->firmware_buf[init_step], mapped_file, file_length); - pfirmware->firmware_buf_size[init_step] = file_length; - } - break; - - default: - break; - } - - - }else if(rst_opt == OPT_FIRMWARE_RESET ) { - /* we only need to download data.img here */ - mapped_file = pfirmware->firmware_buf[init_step]; - file_length = pfirmware->firmware_buf_size[init_step]; - } - - /* Download image file */ - /* The firmware download process is just as following, - * 1. that is each packet will be segmented and inserted to the wait queue. - * 2. each packet segment will be put in the skb_buff packet. - * 3. each skb_buff packet data content will already include the firmware info - * and Tx descriptor info - * */ - rt_status = fw_download_code(dev,mapped_file,file_length); - - if(rt_status != TRUE) { - goto download_firmware_fail; - } - - switch(init_step) { - case FW_INIT_STEP0_BOOT: - /* Download boot - * initialize command descriptor. - * will set polling bit when firmware code is also configured - */ - pfirmware->firmware_status = FW_STATUS_1_MOVE_BOOT_CODE; -#ifdef RTL8190P - // To initialize IMEM, CPU move code from 0x80000080, hence, we send 0x80 byte packet - rt_status = fwSendNullPacket(dev, RTL8190_CPU_START_OFFSET); - if(rt_status != true) - { - RT_TRACE(COMP_INIT, "fwSendNullPacket() fail ! \n"); - goto download_firmware_fail; - } -#endif - //mdelay(1000); - /* - * To initialize IMEM, CPU move code from 0x80000080, - * hence, we send 0x80 byte packet - */ - break; - - case FW_INIT_STEP1_MAIN: - /* Download firmware code. Wait until Boot Ready and Turn on CPU */ - pfirmware->firmware_status = FW_STATUS_2_MOVE_MAIN_CODE; - - /* Check Put Code OK and Turn On CPU */ - rt_status = CPUcheck_maincodeok_turnonCPU(dev); - if(rt_status != TRUE) { - RT_TRACE(COMP_ERR, "CPUcheck_maincodeok_turnonCPU fail!\n"); - goto download_firmware_fail; - } - - pfirmware->firmware_status = FW_STATUS_3_TURNON_CPU; - break; - - case FW_INIT_STEP2_DATA: - /* download initial data code */ - pfirmware->firmware_status = FW_STATUS_4_MOVE_DATA_CODE; - mdelay(1); - - rt_status = CPUcheck_firmware_ready(dev); - if(rt_status != TRUE) { - RT_TRACE(COMP_ERR, "CPUcheck_firmware_ready fail(%d)!\n",rt_status); - goto download_firmware_fail; - } - - /* wait until data code is initialized ready.*/ - pfirmware->firmware_status = FW_STATUS_5_READY; - break; - } - } - - RT_TRACE(COMP_FIRMWARE, "Firmware Download Success\n"); - //assert(pfirmware->firmware_status == FW_STATUS_5_READY, ("Firmware Download Fail\n")); - - return rt_status; - -download_firmware_fail: - RT_TRACE(COMP_ERR, "ERR in %s()\n", __FUNCTION__); - rt_status = FALSE; - return rt_status; - -} - -#if 0 -/* - * Procedure: (1) Transform firmware code from little endian to big endian if required. - * (2) Number of bytes in Firmware downloading should be multiple - * of 4 bytes. If length is not multiple of 4 bytes, appending of zeros is required - * - */ -void CmdAppendZeroAndEndianTransform( - u1Byte *pDst, - u1Byte *pSrc, - u2Byte *pLength) -{ - - u2Byte ulAppendBytes = 0, i; - u2Byte ulLength = *pLength; - -//test only - //memset(pDst, 0xcc, 12); - - - /* Transform from little endian to big endian */ -//#if DEV_BUS_TYPE==PCI_INTERFACE -#if 0 - for( i=0 ; i<(*pLength) ; i+=4) - { - if((i+3) < (*pLength)) pDst[i+0] = pSrc[i+3]; - if((i+2) < (*pLength)) pDst[i+1] = pSrc[i+2]; - if((i+1) < (*pLength)) pDst[i+2] = pSrc[i+1]; - if((i+0) < (*pLength)) pDst[i+3] = pSrc[i+0]; - } -#else - pDst += USB_HWDESC_HEADER_LEN; - ulLength -= USB_HWDESC_HEADER_LEN; - - for( i=0 ; i<ulLength ; i+=4) { - if((i+3) < ulLength) pDst[i+0] = pSrc[i+3]; - if((i+2) < ulLength) pDst[i+1] = pSrc[i+2]; - if((i+1) < ulLength) pDst[i+2] = pSrc[i+1]; - if((i+0) < ulLength) pDst[i+3] = pSrc[i+0]; - - } -#endif - - //1(2) Append Zero - if( ((*pLength) % 4) >0) - { - ulAppendBytes = 4-((*pLength) % 4); - - for(i=0 ; i<ulAppendBytes; i++) - pDst[ 4*((*pLength)/4) + i ] = 0x0; - - *pLength += ulAppendBytes; - } -} -#endif - -#if 0 -RT_STATUS -CmdSendPacket( - PADAPTER Adapter, - PRT_TCB pTcb, - PRT_TX_LOCAL_BUFFER pBuf, - u4Byte BufferLen, - u4Byte PacketType, - BOOLEAN bLastInitPacket - ) -{ - s2Byte i; - u1Byte QueueID; - u2Byte firstDesc,curDesc = 0; - u2Byte FragIndex=0, FragBufferIndex=0; - - RT_STATUS rtStatus = RT_STATUS_SUCCESS; - - CmdInitTCB(Adapter, pTcb, pBuf, BufferLen); - - - if(CmdCheckFragment(Adapter, pTcb, pBuf)) - CmdFragmentTCB(Adapter, pTcb); - else - pTcb->FragLength[0] = (u2Byte)pTcb->BufferList[0].Length; - - QueueID=pTcb->SpecifiedQueueID; -#if DEV_BUS_TYPE!=USB_INTERFACE - firstDesc=curDesc=Adapter->NextTxDescToFill[QueueID]; -#endif - -#if DEV_BUS_TYPE!=USB_INTERFACE - if(VacancyTxDescNum(Adapter, QueueID) > pTcb->BufferCount) -#else - if(PlatformIsTxQueueAvailable(Adapter, QueueID, pTcb->BufferCount) && - RTIsListEmpty(&Adapter->TcbWaitQueue[QueueID])) -#endif - { - pTcb->nDescUsed=0; - - for(i=0 ; i<pTcb->BufferCount ; i++) - { - Adapter->HalFunc.TxFillCmdDescHandler( - Adapter, - pTcb, - QueueID, //QueueIndex - curDesc, //index - FragBufferIndex==0, //bFirstSeg - FragBufferIndex==(pTcb->FragBufCount[FragIndex]-1), //bLastSeg - pTcb->BufferList[i].VirtualAddress, //VirtualAddress - pTcb->BufferList[i].PhysicalAddressLow, //PhyAddressLow - pTcb->BufferList[i].Length, //BufferLen - i!=0, //bSetOwnBit - (i==(pTcb->BufferCount-1)) && bLastInitPacket, //bLastInitPacket - PacketType, //DescPacketType - pTcb->FragLength[FragIndex] //PktLen - ); - - if(FragBufferIndex==(pTcb->FragBufCount[FragIndex]-1)) - { // Last segment of the fragment. - pTcb->nFragSent++; - } - - FragBufferIndex++; - if(FragBufferIndex==pTcb->FragBufCount[FragIndex]) - { - FragIndex++; - FragBufferIndex=0; - } - -#if DEV_BUS_TYPE!=USB_INTERFACE - curDesc=(curDesc+1)%Adapter->NumTxDesc[QueueID]; -#endif - pTcb->nDescUsed++; - } - -#if DEV_BUS_TYPE!=USB_INTERFACE - RTInsertTailList(&Adapter->TcbBusyQueue[QueueID], &pTcb->List); - IncrementTxDescToFill(Adapter, QueueID, pTcb->nDescUsed); - Adapter->HalFunc.SetTxDescOWNHandler(Adapter, QueueID, firstDesc); - // TODO: should call poll use QueueID - Adapter->HalFunc.TxPollingHandler(Adapter, TXCMD_QUEUE); -#endif - } - else -#if DEV_BUS_TYPE!=USB_INTERFACE - goto CmdSendPacket_Fail; -#else - { - pTcb->bLastInitPacket = bLastInitPacket; - RTInsertTailList(&Adapter->TcbWaitQueue[pTcb->SpecifiedQueueID], &pTcb->List); - } -#endif - - return rtStatus; - -#if DEV_BUS_TYPE!=USB_INTERFACE -CmdSendPacket_Fail: - rtStatus = RT_STATUS_FAILURE; - return rtStatus; -#endif - -} -#endif - - - - -#if 0 -RT_STATUS -FWSendNullPacket( - IN PADAPTER Adapter, - IN u4Byte Length -) -{ - RT_STATUS rtStatus = RT_STATUS_SUCCESS; - - - PRT_TCB pTcb; - PRT_TX_LOCAL_BUFFER pBuf; - BOOLEAN bLastInitPacket = FALSE; - - PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); - -#if DEV_BUS_TYPE==USB_INTERFACE - Length += USB_HWDESC_HEADER_LEN; -#endif - - //Get TCB and local buffer from common pool. (It is shared by CmdQ, MgntQ, and USB coalesce DataQ) - if(MgntGetBuffer(Adapter, &pTcb, &pBuf)) - { - PlatformZeroMemory(pBuf->Buffer.VirtualAddress, Length); - rtStatus = CmdSendPacket(Adapter, pTcb, pBuf, Length, DESC_PACKET_TYPE_INIT, bLastInitPacket); //0 : always set LastInitPacket to zero -//#if HAL_CODE_BASE != RTL8190HW -// // TODO: for test only -// ReturnTCB(Adapter, pTcb, RT_STATUS_SUCCESS); -//#endif - if(rtStatus == RT_STATUS_FAILURE) - goto CmdSendNullPacket_Fail; - }else - goto CmdSendNullPacket_Fail; - - PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); - return rtStatus; - - -CmdSendNullPacket_Fail: - PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); - rtStatus = RT_STATUS_FAILURE; - RT_ASSERT(rtStatus == RT_STATUS_SUCCESS, ("CmdSendDownloadCode fail !!\n")); - return rtStatus; -} -#endif - - diff --git a/drivers/staging/rtl8192su/r819xU_firmware.h b/drivers/staging/rtl8192su/r819xU_firmware.h deleted file mode 100644 index 10801be014e0..000000000000 --- a/drivers/staging/rtl8192su/r819xU_firmware.h +++ /dev/null @@ -1,106 +0,0 @@ -#ifndef __INC_FIRMWARE_H -#define __INC_FIRMWARE_H - -#define RTL8190_CPU_START_OFFSET 0x80 -/* TODO: this definition is TBD */ -//#define USB_HWDESC_HEADER_LEN 0 - -/* It should be double word alignment */ -//#if DEV_BUS_TYPE==PCI_INTERFACE -//#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) 4*(v/4) - 8 -//#else -#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) (4*(v/4) - 8 - USB_HWDESC_HEADER_LEN) -//#endif - -typedef enum _firmware_init_step{ - FW_INIT_STEP0_BOOT = 0, - FW_INIT_STEP1_MAIN = 1, - FW_INIT_STEP2_DATA = 2, -}firmware_init_step_e; - -typedef enum _opt_rst_type{ - OPT_SYSTEM_RESET = 0, - OPT_FIRMWARE_RESET = 1, -}opt_rst_type_e; - -/* due to rtl8192 firmware */ -typedef enum _desc_packet_type_e{ - DESC_PACKET_TYPE_INIT = 0, - DESC_PACKET_TYPE_NORMAL = 1, -}desc_packet_type_e; - -typedef enum _firmware_source{ - FW_SOURCE_IMG_FILE = 0, - FW_SOURCE_HEADER_FILE = 1, //from header file -}firmware_source_e, *pfirmware_source_e; - -typedef enum _firmware_status{ - FW_STATUS_0_INIT = 0, - FW_STATUS_1_MOVE_BOOT_CODE = 1, - FW_STATUS_2_MOVE_MAIN_CODE = 2, - FW_STATUS_3_TURNON_CPU = 3, - FW_STATUS_4_MOVE_DATA_CODE = 4, - FW_STATUS_5_READY = 5, -}firmware_status_e; - -typedef struct _rt_firmare_seg_container { - u16 seg_size; - u8 *seg_ptr; -}fw_seg_container, *pfw_seg_container; - -#define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 //64k -#define MAX_FW_INIT_STEP 3 -typedef struct _rt_firmware{ - firmware_status_e firmware_status; - u16 cmdpacket_frag_thresold; - u8 firmware_buf[MAX_FW_INIT_STEP][RTL8190_MAX_FIRMWARE_CODE_SIZE]; - u16 firmware_buf_size[MAX_FW_INIT_STEP]; -}rt_firmware, *prt_firmware; - -typedef struct _rt_firmware_info_819xUsb{ - u8 sz_info[16]; -}rt_firmware_info_819xUsb, *prt_firmware_info_819xUsb; - -#if 0 -/* CPU related */ -RT_STATUS -CPUCheckMainCodeOKAndTurnOnCPU( - IN PADAPTER Adapter - ); - -RT_STATUS -CPUCheckFirmwareReady( - IN PADAPTER Adapter - ); - -/* Firmware related */ -VOID -FWInitializeParameters( - IN PADAPTER Adapter - ); - -RT_STATUS -FWSendDownloadCode( - IN PADAPTER Adapter, - IN pu1Byte CodeVirtualAddrress, - IN u4Byte BufferLen - ); - -RT_STATUS -FWSendNullPacket( - IN PADAPTER Adapter, - IN u4Byte Length - ); - -RT_STATUS -CmdSendPacket( - PADAPTER Adapter, - PRT_TCB pTcb, - PRT_TX_LOCAL_BUFFER pBuf, - u4Byte BufferLen, - u4Byte PacketType, - BOOLEAN bLastInitPacket - ); -#endif -#endif - diff --git a/drivers/staging/rtl8192su/r819xU_phy.c b/drivers/staging/rtl8192su/r819xU_phy.c deleted file mode 100644 index 0cc2785123df..000000000000 --- a/drivers/staging/rtl8192su/r819xU_phy.c +++ /dev/null @@ -1,1808 +0,0 @@ -#include "r8192U.h" -#include "r8192U_hw.h" -#include "r819xU_phy.h" -#include "r819xU_phyreg.h" -#include "r8190_rtl8256.h" -#include "r8192U_dm.h" -#include "r819xU_firmware_img.h" - -#include "ieee80211/dot11d.h" -static u32 RF_CHANNEL_TABLE_ZEBRA[] = { - 0, - 0x085c, //2412 1 - 0x08dc, //2417 2 - 0x095c, //2422 3 - 0x09dc, //2427 4 - 0x0a5c, //2432 5 - 0x0adc, //2437 6 - 0x0b5c, //2442 7 - 0x0bdc, //2447 8 - 0x0c5c, //2452 9 - 0x0cdc, //2457 10 - 0x0d5c, //2462 11 - 0x0ddc, //2467 12 - 0x0e5c, //2472 13 - 0x0f72, //2484 -}; - - -#define rtl819XPHY_REG_1T2RArray Rtl8192UsbPHY_REG_1T2RArray -#define rtl819XMACPHY_Array_PG Rtl8192UsbMACPHY_Array_PG -#define rtl819XMACPHY_Array Rtl8192UsbMACPHY_Array -#define rtl819XRadioA_Array Rtl8192UsbRadioA_Array -#define rtl819XRadioB_Array Rtl8192UsbRadioB_Array -#define rtl819XRadioC_Array Rtl8192UsbRadioC_Array -#define rtl819XRadioD_Array Rtl8192UsbRadioD_Array -#define rtl819XAGCTAB_Array Rtl8192UsbAGCTAB_Array - -/****************************************************************************** - *function: This function read BB parameters from Header file we gen, - * and do register read/write - * input: u32 dwBitMask //taget bit pos in the addr to be modified - * output: none - * return: u32 return the shift bit bit position of the mask - * ****************************************************************************/ -u32 rtl8192_CalculateBitShift(u32 dwBitMask) -{ - u32 i; - for (i=0; i<=31; i++) - { - if (((dwBitMask>>i)&0x1) == 1) - break; - } - return i; -} -/****************************************************************************** - *function: This function check different RF type to execute legal judgement. If RF Path is illegal, we will return false. - * input: none - * output: none - * return: 0(illegal, false), 1(legal,true) - * ***************************************************************************/ -u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath) -{ - u8 ret = 1; - struct r8192_priv *priv = ieee80211_priv(dev); - if (priv->rf_type == RF_2T4R) - ret = 0; - else if (priv->rf_type == RF_1T2R) - { - if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B) - ret = 1; - else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D) - ret = 0; - } - return ret; -} -/****************************************************************************** - *function: This function set specific bits to BB register - * input: net_device dev - * u32 dwRegAddr //target addr to be modified - * u32 dwBitMask //taget bit pos in the addr to be modified - * u32 dwData //value to be write - * output: none - * return: none - * notice: - * ****************************************************************************/ -void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData) -{ - - u32 OriginalValue, BitShift, NewValue; - - if(dwBitMask!= bMaskDWord) - {//if not "double word" write - OriginalValue = read_nic_dword(dev, dwRegAddr); - BitShift = rtl8192_CalculateBitShift(dwBitMask); - NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift)); - write_nic_dword(dev, dwRegAddr, NewValue); - }else - write_nic_dword(dev, dwRegAddr, dwData); - return; -} -/****************************************************************************** - *function: This function reads specific bits from BB register - * input: net_device dev - * u32 dwRegAddr //target addr to be readback - * u32 dwBitMask //taget bit pos in the addr to be readback - * output: none - * return: u32 Data //the readback register value - * notice: - * ****************************************************************************/ -u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask) -{ - u32 Ret = 0, OriginalValue, BitShift; - - OriginalValue = read_nic_dword(dev, dwRegAddr); - BitShift = rtl8192_CalculateBitShift(dwBitMask); - Ret =(OriginalValue & dwBitMask) >> BitShift; - - return (Ret); -} -static u32 phy_FwRFSerialRead( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset ); - -static void phy_FwRFSerialWrite( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data); - -/****************************************************************************** - *function: This function read register from RF chip - * input: net_device dev - * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D - * u32 Offset //target address to be read - * output: none - * return: u32 readback value - * notice: There are three types of serial operations:(1) Software serial write.(2)Hardware LSSI-Low Speed Serial Interface.(3)Hardware HSSI-High speed serial write. Driver here need to implement (1) and (2)---need more spec for this information. - * ****************************************************************************/ -u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset) -{ - struct r8192_priv *priv = ieee80211_priv(dev); - u32 ret = 0; - u32 NewOffset = 0; - BB_REGISTER_DEFINITION_T* pPhyReg = &priv->PHYRegDef[eRFPath]; - rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0); - //make sure RF register offset is correct - Offset &= 0x3f; - - //switch page for 8256 RF IC - if (priv->rf_chip == RF_8256) - { - if (Offset >= 31) - { - priv->RfReg0Value[eRFPath] |= 0x140; - //Switch to Reg_Mode2 for Reg 31-45 - rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) ); - //modify offset - NewOffset = Offset -30; - } - else if (Offset >= 16) - { - priv->RfReg0Value[eRFPath] |= 0x100; - priv->RfReg0Value[eRFPath] &= (~0x40); - //Switch to Reg_Mode 1 for Reg16-30 - rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) ); - - NewOffset = Offset - 15; - } - else - NewOffset = Offset; - } - else - { - RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n"); - NewOffset = Offset; - } - //put desired read addr to LSSI control Register - rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset); - //Issue a posedge trigger - // - rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); - rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); - - - // TODO: we should not delay such a long time. Ask help from SD3 - msleep(1); - - ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData); - - - // Switch back to Reg_Mode0; - if(priv->rf_chip == RF_8256) - { - priv->RfReg0Value[eRFPath] &= 0xebf; - - rtl8192_setBBreg( - dev, - pPhyReg->rf3wireOffset, - bMaskDWord, - (priv->RfReg0Value[eRFPath] << 16)); - } - - return ret; - -} - -/****************************************************************************** - *function: This function write data to RF register - * input: net_device dev - * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D - * u32 Offset //target address to be written - * u32 Data //The new register data to be written - * output: none - * return: none - * notice: For RF8256 only. - =========================================================== - *Reg Mode RegCTL[1] RegCTL[0] Note - * (Reg00[12]) (Reg00[10]) - *=========================================================== - *Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf) - *------------------------------------------------------------------ - *Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf) - *------------------------------------------------------------------ - * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf) - *------------------------------------------------------------------ - * ****************************************************************************/ -void rtl8192_phy_RFSerialWrite(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data) -{ - struct r8192_priv *priv = ieee80211_priv(dev); - u32 DataAndAddr = 0, NewOffset = 0; - BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath]; - - Offset &= 0x3f; - //spin_lock_irqsave(&priv->rf_lock, flags); -// down(&priv->rf_sem); - if (priv->rf_chip == RF_8256) - { - - if (Offset >= 31) - { - priv->RfReg0Value[eRFPath] |= 0x140; - rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath] << 16)); - NewOffset = Offset - 30; - } - else if (Offset >= 16) - { - priv->RfReg0Value[eRFPath] |= 0x100; - priv->RfReg0Value[eRFPath] &= (~0x40); - rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16)); - NewOffset = Offset - 15; - } - else - NewOffset = Offset; - } - else - { - RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n"); - NewOffset = Offset; - } - - // Put write addr in [5:0] and write data in [31:16] - DataAndAddr = (Data<<16) | (NewOffset&0x3f); - - // Write Operation - rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); - - - if(Offset==0x0) - priv->RfReg0Value[eRFPath] = Data; - - // Switch back to Reg_Mode0; - if(priv->rf_chip == RF_8256) - { - if(Offset != 0) - { - priv->RfReg0Value[eRFPath] &= 0xebf; - rtl8192_setBBreg( - dev, - pPhyReg->rf3wireOffset, - bMaskDWord, - (priv->RfReg0Value[eRFPath] << 16)); - } - } - //spin_unlock_irqrestore(&priv->rf_lock, flags); -// up(&priv->rf_sem); - return; -} - -/****************************************************************************** - *function: This function set specific bits to RF register - * input: net_device dev - * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D - * u32 RegAddr //target addr to be modified - * u32 BitMask //taget bit pos in the addr to be modified - * u32 Data //value to be write - * output: none - * return: none - * notice: - * ****************************************************************************/ -void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data) -{ - struct r8192_priv *priv = ieee80211_priv(dev); - u32 Original_Value, BitShift, New_Value; -// u8 time = 0; - - if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) - return; - - if (priv->Rf_Mode == RF_OP_By_FW) - { - if (BitMask != bMask12Bits) // RF data is 12 bits only - { - Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr); - BitShift = rtl8192_CalculateBitShift(BitMask); - New_Value = ((Original_Value) & (~BitMask)) | (Data<< BitShift); - - phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value); - }else - phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data); - - udelay(200); - - } - else - { - if (BitMask != bMask12Bits) // RF data is 12 bits only - { - Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr); - BitShift = rtl8192_CalculateBitShift(BitMask); - New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift)); - - rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, New_Value); - }else - rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data); - } - return; -} - -/****************************************************************************** - *function: This function reads specific bits from RF register - * input: net_device dev - * u32 RegAddr //target addr to be readback - * u32 BitMask //taget bit pos in the addr to be readback - * output: none - * return: u32 Data //the readback register value - * notice: - * ****************************************************************************/ -u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask) -{ - u32 Original_Value, Readback_Value, BitShift; - struct r8192_priv *priv = ieee80211_priv(dev); - - - if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) - return 0; - if (priv->Rf_Mode == RF_OP_By_FW) - { - Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr); - BitShift = rtl8192_CalculateBitShift(BitMask); - Readback_Value = (Original_Value & BitMask) >> BitShift; - udelay(200); - return (Readback_Value); - } - else - { - Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr); - BitShift = rtl8192_CalculateBitShift(BitMask); - Readback_Value = (Original_Value & BitMask) >> BitShift; - return (Readback_Value); - } -} -/****************************************************************************** - *function: We support firmware to execute RF-R/W. - * input: dev - * output: none - * return: none - * notice: - * ***************************************************************************/ -static u32 -phy_FwRFSerialRead( - struct net_device* dev, - RF90_RADIO_PATH_E eRFPath, - u32 Offset ) -{ - u32 retValue = 0; - u32 Data = 0; - u8 time = 0; - //DbgPrint("FW RF CTRL\n\r"); - /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can - not execute the scheme in the initial step. Otherwise, RF-R/W will waste - much time. This is only for site survey. */ - // 1. Read operation need not insert data. bit 0-11 - //Data &= bMask12Bits; - // 2. Write RF register address. Bit 12-19 - Data |= ((Offset&0xFF)<<12); - // 3. Write RF path. bit 20-21 - Data |= ((eRFPath&0x3)<<20); - // 4. Set RF read indicator. bit 22=0 - //Data |= 0x00000; - // 5. Trigger Fw to operate the command. bit 31 - Data |= 0x80000000; - // 6. We can not execute read operation if bit 31 is 1. - while (read_nic_dword(dev, QPNR)&0x80000000) - { - // If FW can not finish RF-R/W for more than ?? times. We must reset FW. - if (time++ < 100) - { - //DbgPrint("FW not finish RF-R Time=%d\n\r", time); - udelay(10); - } - else - break; - } - // 7. Execute read operation. - write_nic_dword(dev, QPNR, Data); - // 8. Check if firmawre send back RF content. - while (read_nic_dword(dev, QPNR)&0x80000000) - { - // If FW can not finish RF-R/W for more than ?? times. We must reset FW. - if (time++ < 100) - { - //DbgPrint("FW not finish RF-W Time=%d\n\r", time); - udelay(10); - } - else - return (0); - } - retValue = read_nic_dword(dev, RF_DATA); - - return (retValue); - -} /* phy_FwRFSerialRead */ - -/****************************************************************************** - *function: We support firmware to execute RF-R/W. - * input: dev - * output: none - * return: none - * notice: - * ***************************************************************************/ -static void -phy_FwRFSerialWrite( - struct net_device* dev, - RF90_RADIO_PATH_E eRFPath, - u32 Offset, - u32 Data ) -{ - u8 time = 0; - - //DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data); - /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can - not execute the scheme in the initial step. Otherwise, RF-R/W will waste - much time. This is only for site survey. */ - - // 1. Set driver write bit and 12 bit data. bit 0-11 - //Data &= bMask12Bits; // Done by uper layer. - // 2. Write RF register address. bit 12-19 - Data |= ((Offset&0xFF)<<12); - // 3. Write RF path. bit 20-21 - Data |= ((eRFPath&0x3)<<20); - // 4. Set RF write indicator. bit 22=1 - Data |= 0x400000; - // 5. Trigger Fw to operate the command. bit 31=1 - Data |= 0x80000000; - - // 6. Write operation. We can not write if bit 31 is 1. - while (read_nic_dword(dev, QPNR)&0x80000000) - { - // If FW can not finish RF-R/W for more than ?? times. We must reset FW. - if (time++ < 100) - { - //DbgPrint("FW not finish RF-W Time=%d\n\r", time); - udelay(10); - } - else - break; - } - // 7. No matter check bit. We always force the write. Because FW will - // not accept the command. - write_nic_dword(dev, QPNR, Data); - /* 2007/11/02 MH Acoording to test, we must delay 20us to wait firmware - to finish RF write operation. */ - /* 2008/01/17 MH We support delay in firmware side now. */ - //delay_us(20); - -} /* phy_FwRFSerialWrite */ - - -/****************************************************************************** - *function: This function read BB parameters from Header file we gen, - * and do register read/write - * input: dev - * output: none - * return: none - * notice: BB parameters may change all the time, so please make - * sure it has been synced with the newest. - * ***************************************************************************/ -void rtl8192_phy_configmac(struct net_device* dev) -{ - u32 dwArrayLen = 0, i; - u32* pdwArray = NULL; - struct r8192_priv *priv = ieee80211_priv(dev); - - if(priv->btxpowerdata_readfromEEPORM) - { - RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n"); - dwArrayLen = MACPHY_Array_PGLength; - pdwArray = rtl819XMACPHY_Array_PG; - - } - else - { - RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array\n"); - dwArrayLen = MACPHY_ArrayLength; - pdwArray = rtl819XMACPHY_Array; - } - for(i = 0; i<dwArrayLen; i=i+3){ - if(pdwArray[i] == 0x318) - { - pdwArray[i+2] = 0x00000800; - //DbgPrint("ptrArray[i], ptrArray[i+1], ptrArray[i+2] = %x, %x, %x\n", - // ptrArray[i], ptrArray[i+1], ptrArray[i+2]); - } - - RT_TRACE(COMP_DBG, "The Rtl8190MACPHY_Array[0] is %x Rtl8190MACPHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n", - pdwArray[i], pdwArray[i+1], pdwArray[i+2]); - rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1], pdwArray[i+2]); - } - return; - -} - -/****************************************************************************** - *function: This function do dirty work - * input: dev - * output: none - * return: none - * notice: BB parameters may change all the time, so please make - * sure it has been synced with the newest. - * ***************************************************************************/ - -void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType) -{ - u32 i; - -#ifdef TO_DO_LIST - u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL; - if(Adapter->bInHctTest) - { - PHY_REGArrayLen = PHY_REGArrayLengthDTM; - AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM; - Rtl8190PHY_REGArray_Table = Rtl819XPHY_REGArrayDTM; - Rtl8190AGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM; - } -#endif - if (ConfigType == BaseBand_Config_PHY_REG) - { - for (i=0; i<PHY_REG_1T2RArrayLength; i+=2) - { - rtl8192_setBBreg(dev, rtl819XPHY_REG_1T2RArray[i], bMaskDWord, rtl819XPHY_REG_1T2RArray[i+1]); - RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x \n",i, rtl819XPHY_REG_1T2RArray[i], rtl819XPHY_REG_1T2RArray[i+1]); - } - } - else if (ConfigType == BaseBand_Config_AGC_TAB) - { - for (i=0; i<AGCTAB_ArrayLength; i+=2) - { - rtl8192_setBBreg(dev, rtl819XAGCTAB_Array[i], bMaskDWord, rtl819XAGCTAB_Array[i+1]); - RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x \n",i, rtl819XAGCTAB_Array[i], rtl819XAGCTAB_Array[i+1]); - } - } - return; - - -} -/****************************************************************************** - *function: This function initialize Register definition offset for Radio Path - * A/B/C/D - * input: net_device dev - * output: none - * return: none - * notice: Initialization value here is constant and it should never be changed - * ***************************************************************************/ -void rtl8192_InitBBRFRegDef(struct net_device* dev) -{ - struct r8192_priv *priv = ieee80211_priv(dev); -// RF Interface Sowrtware Control - priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870 - priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) - priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874 - priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) - - // RF Interface Readback Value - priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0 - priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) - priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4 - priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) - - // RF Interface Output (and Enable) - priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860 - priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864 - priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x868 - priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x86C - - // RF Interface (Output and) Enable - priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) - priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) - priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A) - priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E) - - //Addr of LSSI. Wirte RF register by driver - priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter - priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; - priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter; - priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter; - - // RF parameter - priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; //BB Band Select - priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter; - priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter; - priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; - - // Tx AGC Gain Stage (same for all path. Should we remove this?) - priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage - priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage - priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage - priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage - - // Tranceiver A~D HSSI Parameter-1 - priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; //wire control parameter1 - priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; //wire control parameter1 - priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; //wire control parameter1 - priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; //wire control parameter1 - - // Tranceiver A~D HSSI Parameter-2 - priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; //wire control parameter2 - priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; //wire control parameter2 - priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; //wire control parameter2 - priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; //wire control parameter1 - - // RF switch Control - priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control - priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl; - priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl; - priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl; - - // AGC control 1 - priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; - priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1; - priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1; - priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1; - - // AGC control 2 - priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2; - priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2; - priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2; - priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2; - - // RX AFE control 1 - priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance; - priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance; - priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance; - priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance; - - // RX AFE control 1 - priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE; - priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE; - priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE; - priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE; - - // Tx AFE control 1 - priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance; - priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance; - priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance; - priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance; - - // Tx AFE control 2 - priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE; - priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE; - priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE; - priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE; - - // Tranceiver LSSI Readback - priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; - priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; - priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack; - priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; - -} -/****************************************************************************** - *function: This function is to write register and then readback to make sure whether BB and RF is OK - * input: net_device dev - * HW90_BLOCK_E CheckBlock - * RF90_RADIO_PATH_E eRFPath //only used when checkblock is HW90_BLOCK_RF - * output: none - * return: return whether BB and RF is ok(0:OK; 1:Fail) - * notice: This function may be removed in the ASIC - * ***************************************************************************/ -u8 rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath) -{ -// struct r8192_priv *priv = ieee80211_priv(dev); -// BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath]; - u8 ret = 0; - u32 i, CheckTimes = 4, dwRegRead = 0; - u32 WriteAddr[4]; - u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f}; - // Initialize register address offset to be checked - WriteAddr[HW90_BLOCK_MAC] = 0x100; - WriteAddr[HW90_BLOCK_PHY0] = 0x900; - WriteAddr[HW90_BLOCK_PHY1] = 0x800; - WriteAddr[HW90_BLOCK_RF] = 0x3; - RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __FUNCTION__, CheckBlock); - for(i=0 ; i < CheckTimes ; i++) - { - - // - // Write Data to register and readback - // - switch(CheckBlock) - { - case HW90_BLOCK_MAC: - RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write 0x100 here!"); - break; - - case HW90_BLOCK_PHY0: - case HW90_BLOCK_PHY1: - write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]); - dwRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]); - break; - - case HW90_BLOCK_RF: - WriteData[i] &= 0xfff; - rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits, WriteData[i]); - // TODO: we should not delay for such a long time. Ask SD3 - msleep(1); - dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits); - msleep(1); - break; - - default: - ret = 1; - break; - } - - - // - // Check whether readback data is correct - // - if(dwRegRead != WriteData[i]) - { - RT_TRACE((COMP_PHY|COMP_ERR), "====>error=====dwRegRead: %x, WriteData: %x \n", dwRegRead, WriteData[i]); - ret = 1; - break; - } - } - - return ret; -} - - -/****************************************************************************** - *function: This function initialize BB&RF - * input: net_device dev - * output: none - * return: none - * notice: Initialization value may change all the time, so please make - * sure it has been synced with the newest. - * ***************************************************************************/ -void rtl8192_BB_Config_ParaFile(struct net_device* dev) -{ - struct r8192_priv *priv = ieee80211_priv(dev); - u8 bRegValue = 0, eCheckItem = 0, rtStatus = 0; - u32 dwRegValue = 0; - /************************************** - //<1>Initialize BaseBand - **************************************/ - - /*--set BB Global Reset--*/ - bRegValue = read_nic_byte(dev, BB_GLOBAL_RESET); - write_nic_byte(dev, BB_GLOBAL_RESET,(bRegValue|BB_GLOBAL_RESET_BIT)); - mdelay(50); - /*---set BB reset Active---*/ - dwRegValue = read_nic_dword(dev, CPU_GEN); - write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST))); - - /*----Ckeck FPGAPHY0 and PHY1 board is OK----*/ - // TODO: this function should be removed on ASIC , Emily 2007.2.2 - for(eCheckItem=(HW90_BLOCK_E)HW90_BLOCK_PHY0; eCheckItem<=HW90_BLOCK_PHY1; eCheckItem++) - { - rtStatus = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem, (RF90_RADIO_PATH_E)0); //don't care RF path - if(rtStatus != 0) - { - RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():Check PHY%d Fail!!\n", eCheckItem-1); - return ; - } - } - /*---- Set CCK and OFDM Block "OFF"----*/ - rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); - /*----BB Register Initilazation----*/ - //==m==>Set PHY REG From Header<==m== - rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG); - - /*----Set BB reset de-Active----*/ - dwRegValue = read_nic_dword(dev, CPU_GEN); - write_nic_dword(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST)); - - /*----BB AGC table Initialization----*/ - //==m==>Set PHY REG From Header<==m== - rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB); - - /*----Enable XSTAL ----*/ - write_nic_byte_E(dev, 0x5e, 0x00); - if (priv->card_8192_version == (u8)VERSION_819xU_A) - { - //Antenna gain offset from B/C/D to A - dwRegValue = (priv->AntennaTxPwDiff[1]<<4 | priv->AntennaTxPwDiff[0]); - rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC), dwRegValue); - - //XSTALLCap - dwRegValue = priv->CrystalCap & 0xf; - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap, dwRegValue); - } - - // Check if the CCK HighPower is turned ON. - // This is used to calculate PWDB. - priv->bCckHighPower = (u8)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200)); - return; -} -/****************************************************************************** - *function: This function initialize BB&RF - * input: net_device dev - * output: none - * return: none - * notice: Initialization value may change all the time, so please make - * sure it has been synced with the newest. - * ***************************************************************************/ -void rtl8192_BBConfig(struct net_device* dev) -{ - rtl8192_InitBBRFRegDef(dev); - //config BB&RF. As hardCode based initialization has not been well - //implemented, so use file first.FIXME:should implement it for hardcode? - rtl8192_BB_Config_ParaFile(dev); - return; -} - -/****************************************************************************** - *function: This function obtains the initialization value of Tx power Level offset - * input: net_device dev - * output: none - * return: none - * ***************************************************************************/ -void rtl8192_phy_getTxPower(struct net_device* dev) -{ - struct r8192_priv *priv = ieee80211_priv(dev); - priv->MCSTxPowerLevelOriginalOffset[0] = - read_nic_dword(dev, rTxAGC_Rate18_06); - priv->MCSTxPowerLevelOriginalOffset[1] = - read_nic_dword(dev, rTxAGC_Rate54_24); - priv->MCSTxPowerLevelOriginalOffset[2] = - read_nic_dword(dev, rTxAGC_Mcs03_Mcs00); - priv->MCSTxPowerLevelOriginalOffset[3] = - read_nic_dword(dev, rTxAGC_Mcs07_Mcs04); - priv->MCSTxPowerLevelOriginalOffset[4] = - read_nic_dword(dev, rTxAGC_Mcs11_Mcs08); - priv->MCSTxPowerLevelOriginalOffset[5] = - read_nic_dword(dev, rTxAGC_Mcs15_Mcs12); - - // read rx initial gain - priv->DefaultInitialGain[0] = read_nic_byte(dev, rOFDM0_XAAGCCore1); - priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1); - priv->DefaultInitialGain[2] = read_nic_byte(dev, rOFDM0_XCAGCCore1); - priv->DefaultInitialGain[3] = read_nic_byte(dev, rOFDM0_XDAGCCore1); - RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n", - priv->DefaultInitialGain[0], priv->DefaultInitialGain[1], - priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]); - - // read framesync - priv->framesync = read_nic_byte(dev, rOFDM0_RxDetector3); - priv->framesyncC34 = read_nic_byte(dev, rOFDM0_RxDetector2); - RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n", - rOFDM0_RxDetector3, priv->framesync); - - // read SIFS (save the value read fome MACPHY_REG.txt) - priv->SifsTime = read_nic_word(dev, SIFS); - - return; -} - -/****************************************************************************** - *function: This function obtains the initialization value of Tx power Level offset - * input: net_device dev - * output: none - * return: none - * ***************************************************************************/ -void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel) -{ - struct r8192_priv *priv = ieee80211_priv(dev); - u8 powerlevel = priv->TxPowerLevelCCK[channel-1]; - u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; - - switch(priv->rf_chip) - { - case RF_8256: - PHY_SetRF8256CCKTxPower(dev, powerlevel); //need further implement - PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G); - break; - default: -// case RF_8225: -// case RF_8258: - RT_TRACE((COMP_PHY|COMP_ERR), "error RF chipID(8225 or 8258) in function %s()\n", __FUNCTION__); - break; - } - return; -} - -/****************************************************************************** - *function: This function check Rf chip to do RF config - * input: net_device dev - * output: none - * return: only 8256 is supported - * ***************************************************************************/ -void rtl8192_phy_RFConfig(struct net_device* dev) -{ - struct r8192_priv *priv = ieee80211_priv(dev); - - switch(priv->rf_chip) - { - case RF_8256: - PHY_RF8256_Config(dev); - break; - // case RF_8225: - // case RF_8258: - default: - RT_TRACE(COMP_ERR, "error chip id\n"); - break; - } - return; -} - -/****************************************************************************** - *function: This function update Initial gain - * input: net_device dev - * output: none - * return: As Windows has not implemented this, wait for complement - * ***************************************************************************/ -void rtl8192_phy_updateInitGain(struct net_device* dev) -{ - return; -} - -/****************************************************************************** - *function: This function read RF parameters from general head file, and do RF 3-wire - * input: net_device dev - * output: none - * return: return code show if RF configuration is successful(0:pass, 1:fail) - * Note: Delay may be required for RF configuration - * ***************************************************************************/ -u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath) -{ - - int i; - //u32* pRFArray; - u8 ret = 0; - - switch(eRFPath){ - case RF90_PATH_A: - for(i = 0;i<RadioA_ArrayLength; i=i+2){ - - if(rtl819XRadioA_Array[i] == 0xfe){ - mdelay(100); - continue; - } - rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioA_Array[i], bMask12Bits, rtl819XRadioA_Array[i+1]); - mdelay(1); - - } - break; - case RF90_PATH_B: - for(i = 0;i<RadioB_ArrayLength; i=i+2){ - - if(rtl819XRadioB_Array[i] == 0xfe){ - mdelay(100); - continue; - } - rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioB_Array[i], bMask12Bits, rtl819XRadioB_Array[i+1]); - mdelay(1); - - } - break; - case RF90_PATH_C: - for(i = 0;i<RadioC_ArrayLength; i=i+2){ - - if(rtl819XRadioC_Array[i] == 0xfe){ - mdelay(100); - continue; - } - rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioC_Array[i], bMask12Bits, rtl819XRadioC_Array[i+1]); - mdelay(1); - - } - break; - case RF90_PATH_D: - for(i = 0;i<RadioD_ArrayLength; i=i+2){ - - if(rtl819XRadioD_Array[i] == 0xfe){ - mdelay(100); - continue; - } - rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioD_Array[i], bMask12Bits, rtl819XRadioD_Array[i+1]); - mdelay(1); - - } - break; - default: - break; - } - - return ret;; - -} -/****************************************************************************** - *function: This function set Tx Power of the channel - * input: struct net_device *dev - * u8 channel - * output: none - * return: none - * Note: - * ***************************************************************************/ -void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel) -{ - struct r8192_priv *priv = ieee80211_priv(dev); - u8 powerlevel = priv->TxPowerLevelCCK[channel-1]; - u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; - - switch(priv->rf_chip) - { - case RF_8225: -#ifdef TO_DO_LIST - PHY_SetRF8225CckTxPower(Adapter, powerlevel); - PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G); -#endif - break; - - case RF_8256: - PHY_SetRF8256CCKTxPower(dev, powerlevel); - PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G); - break; - - case RF_8258: - break; - default: - RT_TRACE(COMP_ERR, "unknown rf chip ID in rtl8192_SetTxPowerLevel()\n"); - break; - } - return; -} - -/****************************************************************************** - *function: This function set RF state on or off - * input: struct net_device *dev - * RT_RF_POWER_STATE eRFPowerState //Power State to set - * output: none - * return: none - * Note: - * ***************************************************************************/ -bool rtl8192_SetRFPowerState(struct net_device *dev, RT_RF_POWER_STATE eRFPowerState) -{ - bool bResult = true; -// u8 eRFPath; - struct r8192_priv *priv = ieee80211_priv(dev); - - if(eRFPowerState == priv->ieee80211->eRFPowerState) - return false; - - if(priv->SetRFPowerStateInProgress == true) - return false; - - priv->SetRFPowerStateInProgress = true; - - switch(priv->rf_chip) - { - case RF_8256: - switch( eRFPowerState ) - { - case eRfOn: -#if 0 - rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); // 0x860[4] - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); // 0x88c[4] - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5] - rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x3); // 0xc04[3:0] - rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x3); // 0xd04[3:0] - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0x7000, 0x3); // 0x884[14:12] - // for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++) - // PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x2); - - //SwChnl(Adapter->ChannelID); -#endif - //RF-A, RF-B - //enable RF-Chip A/B - rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); // 0x860[4] - //analog to digital on - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8] - //digital to analog on - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x3); // 0x880[4:3] - //rx antenna on - rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3);// 0xc04[1:0] - //rx antenna on - rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3);// 0xd04[1:0] - //analog to digital part2 on - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5] - - break; - - case eRfSleep: - - break; - - case eRfOff: -#if 0 - rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); // 0x860[4] - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x0); // 0x88c[4] - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); // 0x880[6:5] - rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0); // 0xc04[3:0] - rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0); // 0xd04[3:0] - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0x7000, 0x0); // 0x884[14:12] - // for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++) - // PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x0); -#endif - //RF-A, RF-B - //disable RF-Chip A/B - rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); // 0x860[4] - //analog to digital off, for power save - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8] - //digital to analog off, for power save - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0); // 0x880[4:3] - //rx antenna off - rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);// 0xc04[3:0] - //rx antenna off - rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);// 0xd04[3:0] - //analog to digital part2 off, for power save - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); // 0x880[6:5] - - break; - - default: - bResult = false; - RT_TRACE(COMP_ERR, "SetRFPowerState819xUsb(): unknow state to set: 0x%X!!!\n", eRFPowerState); - break; - } - break; - default: - RT_TRACE(COMP_ERR, "Not support rf_chip(%x)\n", priv->rf_chip); - break; - } -#ifdef TO_DO_LIST - if(bResult) - { - // Update current RF state variable. - pHalData->eRFPowerState = eRFPowerState; - switch(pHalData->RFChipID ) - { - case RF_8256: - switch(pHalData->eRFPowerState) - { - case eRfOff: - // - //If Rf off reason is from IPS, Led should blink with no link, by Maddest 071015 - // - if(pMgntInfo->RfOffReason==RF_CHANGE_BY_IPS ) - { - Adapter->HalFunc.LedControlHandler(Adapter,LED_CTL_NO_LINK); - } - else - { - // Turn off LED if RF is not ON. - Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_POWER_OFF); - } - break; - - case eRfOn: - // Turn on RF we are still linked, which might happen when - // we quickly turn off and on HW RF. 2006.05.12, by rcnjko. - if( pMgntInfo->bMediaConnect == TRUE ) - { - Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_LINK); - } - else - { - // Turn off LED if RF is not ON. - Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK); - } - break; - - default: - // do nothing. - break; - }// Switch RF state - break; - - default: - RT_TRACE(COMP_RF, DBG_LOUD, ("SetRFPowerState8190(): Unknown RF type\n")); - break; - } - - } -#endif - priv->SetRFPowerStateInProgress = false; - - return bResult; -} - -/**************************************************************************************** - *function: This function set command table variable(struct SwChnlCmd). - * input: SwChnlCmd* CmdTable //table to be set. - * u32 CmdTableIdx //variable index in table to be set - * u32 CmdTableSz //table size. - * SwChnlCmdID CmdID //command ID to set. - * u32 Para1 - * u32 Para2 - * u32 msDelay - * output: - * return: true if finished, false otherwise - * Note: - * ************************************************************************************/ -u8 rtl8192_phy_SetSwChnlCmdArray( - SwChnlCmd* CmdTable, - u32 CmdTableIdx, - u32 CmdTableSz, - SwChnlCmdID CmdID, - u32 Para1, - u32 Para2, - u32 msDelay - ) -{ - SwChnlCmd* pCmd; - - if(CmdTable == NULL) - { - RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n"); - return false; - } - if(CmdTableIdx >= CmdTableSz) - { - RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n", - CmdTableIdx, CmdTableSz); - return false; - } - - pCmd = CmdTable + CmdTableIdx; - pCmd->CmdID = CmdID; - pCmd->Para1 = Para1; - pCmd->Para2 = Para2; - pCmd->msDelay = msDelay; - - return true; -} -/****************************************************************************** - *function: This function set channel step by step - * input: struct net_device *dev - * u8 channel - * u8* stage //3 stages - * u8* step // - * u32* delay //whether need to delay - * output: store new stage, step and delay for next step(combine with function above) - * return: true if finished, false otherwise - * Note: Wait for simpler function to replace it //wb - * ***************************************************************************/ -u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* stage, u8* step, u32* delay) -{ - struct r8192_priv *priv = ieee80211_priv(dev); -// PCHANNEL_ACCESS_SETTING pChnlAccessSetting; - SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT]; - u32 PreCommonCmdCnt; - SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT]; - u32 PostCommonCmdCnt; - SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT]; - u32 RfDependCmdCnt; - SwChnlCmd *CurrentCmd = NULL; - //RF90_RADIO_PATH_E eRFPath; - u8 eRFPath; -// u32 RfRetVal; -// u8 RetryCnt; - - RT_TRACE(COMP_CH, "====>%s()====stage:%d, step:%d, channel:%d\n", __FUNCTION__, *stage, *step, channel); -// RT_ASSERT(IsLegalChannel(Adapter, channel), ("illegal channel: %d\n", channel)); - if (!IsLegalChannel(priv->ieee80211, channel)) - { - RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel); - return true; //return true to tell upper caller function this channel setting is finished! Or it will in while loop. - } -//FIXME:need to check whether channel is legal or not here.WB - - - //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++) -// for(eRFPath = 0; eRFPath <RF90_PATH_MAX; eRFPath++) -// { -// if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) -// continue; - // <1> Fill up pre common command. - PreCommonCmdCnt = 0; - rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT, - CmdID_SetTxPowerLevel, 0, 0, 0); - rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT, - CmdID_End, 0, 0, 0); - - // <2> Fill up post common command. - PostCommonCmdCnt = 0; - - rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT, - CmdID_End, 0, 0, 0); - - // <3> Fill up RF dependent command. - RfDependCmdCnt = 0; - switch( priv->rf_chip ) - { - case RF_8225: - if (!(channel >= 1 && channel <= 14)) - { - RT_TRACE(COMP_ERR, "illegal channel for Zebra 8225: %d\n", channel); - return true; - } - rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, - CmdID_RF_WriteReg, rZebra1_Channel, RF_CHANNEL_TABLE_ZEBRA[channel], 10); - rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, - CmdID_End, 0, 0, 0); - break; - - case RF_8256: - // TEST!! This is not the table for 8256!! - if (!(channel >= 1 && channel <= 14)) - { - RT_TRACE(COMP_ERR, "illegal channel for Zebra 8256: %d\n", channel); - return true; - } - rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, - CmdID_RF_WriteReg, rZebra1_Channel, channel, 10); - rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, - CmdID_End, 0, 0, 0); - break; - - case RF_8258: - break; - - default: - RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip); - return true; - break; - } - - - do{ - switch(*stage) - { - case 0: - CurrentCmd=&PreCommonCmd[*step]; - break; - case 1: - CurrentCmd=&RfDependCmd[*step]; - break; - case 2: - CurrentCmd=&PostCommonCmd[*step]; - break; - } - - if(CurrentCmd->CmdID==CmdID_End) - { - if((*stage)==2) - { - (*delay)=CurrentCmd->msDelay; - return true; - } - else - { - (*stage)++; - (*step)=0; - continue; - } - } - - switch(CurrentCmd->CmdID) - { - case CmdID_SetTxPowerLevel: - if(priv->card_8192_version == (u8)VERSION_819xU_A) //xiong: consider it later! - rtl8192_SetTxPowerLevel(dev,channel); - break; - case CmdID_WritePortUlong: - write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2); - break; - case CmdID_WritePortUshort: - write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2); - break; - case CmdID_WritePortUchar: - write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2); - break; - case CmdID_RF_WriteReg: - for(eRFPath = 0; eRFPath < RF90_PATH_MAX; eRFPath++) - { - rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bZebra1_ChannelNum, CurrentCmd->Para2); - } - break; - default: - break; - } - - break; - }while(true); -// }/*for(Number of RF paths)*/ - - (*delay)=CurrentCmd->msDelay; - (*step)++; - return false; -} - -/****************************************************************************** - *function: This function does acturally set channel work - * input: struct net_device *dev - * u8 channel - * output: none - * return: noin - * Note: We should not call this function directly - * ***************************************************************************/ -void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel) -{ - struct r8192_priv *priv = ieee80211_priv(dev); - u32 delay = 0; - - while(!rtl8192_phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay)) - { - // if(delay>0) - // msleep(delay);//or mdelay? need further consideration - if(!priv->up) - break; - } -} -/****************************************************************************** - *function: Callback routine of the work item for switch channel. - * input: - * - * output: none - * return: noin - * ***************************************************************************/ -void rtl8192_SwChnl_WorkItem(struct net_device *dev) -{ - - struct r8192_priv *priv = ieee80211_priv(dev); - - RT_TRACE(COMP_CH, "==> SwChnlCallback819xUsbWorkItem(), chan:%d\n", priv->chan); - - - rtl8192_phy_FinishSwChnlNow(dev , priv->chan); - - RT_TRACE(COMP_CH, "<== SwChnlCallback819xUsbWorkItem()\n"); -} - -/****************************************************************************** - *function: This function scheduled actural workitem to set channel - * input: net_device dev - * u8 channel //channel to set - * output: none - * return: return code show if workitem is scheduled(1:pass, 0:fail) - * Note: Delay may be required for RF configuration - * ***************************************************************************/ -u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel) -{ - struct r8192_priv *priv = ieee80211_priv(dev); - RT_TRACE(COMP_CH, "=====>%s(), SwChnlInProgress:%d\n", __FUNCTION__, priv->SwChnlInProgress); - if(!priv->up) - return false; - if(priv->SwChnlInProgress) - return false; - -// if(pHalData->SetBWModeInProgress) -// return; -if (0) //to test current channel from RF reg 0x7. -{ - u8 eRFPath; - for(eRFPath = 0; eRFPath < 2; eRFPath++){ - printk("====>set channel:%x\n",rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x7, bZebra1_ChannelNum)); - udelay(10); - } -} - //-------------------------------------------- - switch(priv->ieee80211->mode) - { - case WIRELESS_MODE_A: - case WIRELESS_MODE_N_5G: - if (channel<=14){ - RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14"); - return false; - } - break; - case WIRELESS_MODE_B: - if (channel>14){ - RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14"); - return false; - } - break; - case WIRELESS_MODE_G: - case WIRELESS_MODE_N_24G: - if (channel>14){ - RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14"); - return false; - } - break; - } - //-------------------------------------------- - - priv->SwChnlInProgress = true; - if(channel == 0) - channel = 1; - - priv->chan=channel; - - priv->SwChnlStage=0; - priv->SwChnlStep=0; -// schedule_work(&(priv->SwChnlWorkItem)); -// rtl8192_SwChnl_WorkItem(dev); - if(priv->up) { -// queue_work(priv->priv_wq,&(priv->SwChnlWorkItem)); - rtl8192_SwChnl_WorkItem(dev); - } - - priv->SwChnlInProgress = false; - return true; -} - - -// -/****************************************************************************** - *function: Callback routine of the work item for set bandwidth mode. - * input: struct net_device *dev - * HT_CHANNEL_WIDTH Bandwidth //20M or 40M - * HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care - * output: none - * return: none - * Note: I doubt whether SetBWModeInProgress flag is necessary as we can - * test whether current work in the queue or not.//do I? - * ***************************************************************************/ -void rtl8192_SetBWModeWorkItem(struct net_device *dev) -{ - - struct r8192_priv *priv = ieee80211_priv(dev); - u8 regBwOpMode; - - RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem() Switch to %s bandwidth\n", \ - priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz") - - - if(priv->rf_chip == RF_PSEUDO_11N) - { - priv->SetBWModeInProgress= false; - return; - } - - //<1>Set MAC register - regBwOpMode = read_nic_byte(dev, BW_OPMODE); - - switch(priv->CurrentChannelBW) - { - case HT_CHANNEL_WIDTH_20: - regBwOpMode |= BW_OPMODE_20MHZ; - // 2007/02/07 Mark by Emily becasue we have not verify whether this register works - write_nic_byte(dev, BW_OPMODE, regBwOpMode); - break; - - case HT_CHANNEL_WIDTH_20_40: - regBwOpMode &= ~BW_OPMODE_20MHZ; - // 2007/02/07 Mark by Emily becasue we have not verify whether this register works - write_nic_byte(dev, BW_OPMODE, regBwOpMode); - break; - - default: - RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",priv->CurrentChannelBW); - break; - } - - //<2>Set PHY related register - switch(priv->CurrentChannelBW) - { - case HT_CHANNEL_WIDTH_20: - // Add by Vivi 20071119 - rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); - rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1); - - // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207 -#if 0 - write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000); - write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317); - write_nic_dword(dev, rCCK0_DebugPort, 0x00000204); -#endif - priv->cck_present_attentuation = - priv->cck_present_attentuation_20Mdefault + priv->cck_present_attentuation_difference; - - if(priv->cck_present_attentuation > 22) - priv->cck_present_attentuation= 22; - if(priv->cck_present_attentuation< 0) - priv->cck_present_attentuation = 0; - RT_TRACE(COMP_INIT, "20M, pHalData->CCKPresentAttentuation = %d\n", priv->cck_present_attentuation); - - if(priv->chan == 14 && !priv->bcck_in_ch14) - { - priv->bcck_in_ch14 = TRUE; - dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); - } - else if(priv->chan != 14 && priv->bcck_in_ch14) - { - priv->bcck_in_ch14 = FALSE; - dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); - } - else - dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); - - break; - case HT_CHANNEL_WIDTH_20_40: - // Add by Vivi 20071119 - rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); - rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); - rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1)); - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); - rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC); -#if 0 - // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207 - write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000); - write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e); - write_nic_dword(dev, rCCK0_DebugPort, 0x00000409); -#endif - priv->cck_present_attentuation = - priv->cck_present_attentuation_40Mdefault + priv->cck_present_attentuation_difference; - - if(priv->cck_present_attentuation > 22) - priv->cck_present_attentuation = 22; - if(priv->cck_present_attentuation < 0) - priv->cck_present_attentuation = 0; - - RT_TRACE(COMP_INIT, "40M, pHalData->CCKPresentAttentuation = %d\n", priv->cck_present_attentuation); - if(priv->chan == 14 && !priv->bcck_in_ch14) - { - priv->bcck_in_ch14 = true; - dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); - } - else if(priv->chan!= 14 && priv->bcck_in_ch14) - { - priv->bcck_in_ch14 = false; - dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); - } - else - dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); - - break; - default: - RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n" ,priv->CurrentChannelBW); - break; - - } - //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315 - -#if 1 - //<3>Set RF related register - switch( priv->rf_chip ) - { - case RF_8225: -#ifdef TO_DO_LIST - PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW); -#endif - break; - - case RF_8256: - PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW); - break; - - case RF_8258: - // PHY_SetRF8258Bandwidth(); - break; - - case RF_PSEUDO_11N: - // Do Nothing - break; - - default: - RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip); - break; - } -#endif - priv->SetBWModeInProgress= false; - - RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb(), %d", atomic_read(&(priv->ieee80211->atm_swbw)) ); -} - -/****************************************************************************** - *function: This function schedules bandwith switch work. - * input: struct net_device *dev - * HT_CHANNEL_WIDTH Bandwidth //20M or 40M - * HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care - * output: none - * return: none - * Note: I doubt whether SetBWModeInProgress flag is necessary as we can - * test whether current work in the queue or not.//do I? - * ***************************************************************************/ -void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset) -{ - struct r8192_priv *priv = ieee80211_priv(dev); - - if(priv->SetBWModeInProgress) - return; - priv->SetBWModeInProgress= true; - - priv->CurrentChannelBW = Bandwidth; - - if(Offset==HT_EXTCHNL_OFFSET_LOWER) - priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER; - else if(Offset==HT_EXTCHNL_OFFSET_UPPER) - priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER; - else - priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE; - - //queue_work(priv->priv_wq, &(priv->SetBWModeWorkItem)); - // schedule_work(&(priv->SetBWModeWorkItem)); - rtl8192_SetBWModeWorkItem(dev); - -} - -void InitialGain819xUsb(struct net_device *dev, u8 Operation) -{ - struct r8192_priv *priv = ieee80211_priv(dev); - - priv->InitialGainOperateType = Operation; - - if(priv->up) - { - queue_delayed_work(priv->priv_wq,&priv->initialgain_operate_wq,0); - } -} - -extern void InitialGainOperateWorkItemCallBack(struct work_struct *work) -{ - struct delayed_work *dwork = container_of(work,struct delayed_work,work); - struct r8192_priv *priv = container_of(dwork,struct r8192_priv,initialgain_operate_wq); - struct net_device *dev = priv->ieee80211->dev; -#define SCAN_RX_INITIAL_GAIN 0x17 -#define POWER_DETECTION_TH 0x08 - u32 BitMask; - u8 initial_gain; - u8 Operation; - - Operation = priv->InitialGainOperateType; - - switch(Operation) - { - case IG_Backup: - RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n"); - initial_gain = SCAN_RX_INITIAL_GAIN;//priv->DefaultInitialGain[0];// - BitMask = bMaskByte0; - if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) - rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF - priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask); - priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask); - priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask); - priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask); - BitMask = bMaskByte2; - priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask); - - RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1); - RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1); - RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1); - RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1); - RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca); - - RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain); - write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain); - write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain); - write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain); - write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain); - RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH); - write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH); - break; - case IG_Restore: - RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n"); - BitMask = 0x7f; //Bit0~ Bit6 - if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) - rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF - - rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1); - rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1); - rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1); - rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1); - BitMask = bMaskByte2; - rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca); - - RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1); - RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1); - RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1); - RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1); - RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca); - -#ifdef RTL8190P - SetTxPowerLevel8190(Adapter,priv->CurrentChannel); -#endif -#ifdef RTL8192E - SetTxPowerLevel8190(Adapter,priv->CurrentChannel); -#endif -//#ifdef RTL8192U - rtl8192_phy_setTxPower(dev,priv->ieee80211->current_network.channel); -//#endif - - if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) - rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // FW DIG ON - break; - default: - RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n"); - break; - } -} - diff --git a/drivers/staging/rtl8192su/r819xU_phy.h b/drivers/staging/rtl8192su/r819xU_phy.h deleted file mode 100644 index 3e3bc577e6c3..000000000000 --- a/drivers/staging/rtl8192su/r819xU_phy.h +++ /dev/null @@ -1,90 +0,0 @@ -#ifndef _R819XU_PHY_H -#define _R819XU_PHY_H - -/* Channel switch:The size of command tables for switch channel*/ -#define MAX_PRECMD_CNT 16 -#define MAX_RFDEPENDCMD_CNT 16 -#define MAX_POSTCMD_CNT 16 - -typedef enum _SwChnlCmdID{ - CmdID_End, - CmdID_SetTxPowerLevel, - CmdID_BBRegWrite10, - CmdID_WritePortUlong, - CmdID_WritePortUshort, - CmdID_WritePortUchar, - CmdID_RF_WriteReg, -}SwChnlCmdID; - -/*--------------------------------Define structure--------------------------------*/ -/* 1. Switch channel related */ -typedef struct _SwChnlCmd{ - SwChnlCmdID CmdID; - u32 Para1; - u32 Para2; - u32 msDelay; -}__attribute__ ((packed)) SwChnlCmd; - -extern u32 rtl819XMACPHY_Array_PG[]; -extern u32 rtl819XPHY_REG_1T2RArray[]; -extern u32 rtl819XAGCTAB_Array[]; -extern u32 rtl819XRadioA_Array[]; -extern u32 rtl819XRadioB_Array[]; -extern u32 rtl819XRadioC_Array[]; -extern u32 rtl819XRadioD_Array[]; - -typedef enum _HW90_BLOCK{ - HW90_BLOCK_MAC = 0, - HW90_BLOCK_PHY0 = 1, - HW90_BLOCK_PHY1 = 2, - HW90_BLOCK_RF = 3, - HW90_BLOCK_MAXIMUM = 4, // Never use this -}HW90_BLOCK_E, *PHW90_BLOCK_E; - -typedef enum _RF90_RADIO_PATH{ - RF90_PATH_A = 0, //Radio Path A - RF90_PATH_B = 1, //Radio Path B - RF90_PATH_C = 2, //Radio Path C - RF90_PATH_D = 3, //Radio Path D - RF90_PATH_MAX //Max RF number 92 support -}RF90_RADIO_PATH_E, *PRF90_RADIO_PATH_E; - -#define bMaskByte0 0xff -#define bMaskByte1 0xff00 -#define bMaskByte2 0xff0000 -#define bMaskByte3 0xff000000 -#define bMaskHWord 0xffff0000 -#define bMaskLWord 0x0000ffff -#define bMaskDWord 0xffffffff - -//extern u32 rtl8192_CalculateBitShift(u32 dwBitMask); -extern u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath); -extern void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData); -extern u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask); -//extern u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset); -//extern void rtl8192_phy_RFSerialWrite(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data); -extern void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data); -extern u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask); -extern void rtl8192_phy_configmac(struct net_device* dev); -extern void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType); -//extern void rtl8192_InitBBRFRegDef(struct net_device* dev); -extern u8 rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath); -//extern void rtl8192_BB_Config_ParaFile(struct net_device* dev); -extern void rtl8192_BBConfig(struct net_device* dev); -extern void rtl8192_phy_getTxPower(struct net_device* dev); -extern void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel); -extern void rtl8192_phy_RFConfig(struct net_device* dev); -extern void rtl8192_phy_updateInitGain(struct net_device* dev); -extern u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath); - -extern u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel); -extern void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset); -extern void rtl8192_SwChnl_WorkItem(struct net_device *dev); -void rtl8192_SetBWModeWorkItem(struct net_device *dev); -extern bool rtl8192_SetRFPowerState(struct net_device *dev, RT_RF_POWER_STATE eRFPowerState); -//added by amy -extern void InitialGain819xUsb(struct net_device *dev, u8 Operation); - -extern void InitialGainOperateWorkItemCallBack(struct work_struct *work); - -#endif diff --git a/drivers/staging/rtl8192su/r819xU_phyreg.h b/drivers/staging/rtl8192su/r819xU_phyreg.h deleted file mode 100644 index b62f1a6fb1eb..000000000000 --- a/drivers/staging/rtl8192su/r819xU_phyreg.h +++ /dev/null @@ -1,871 +0,0 @@ -#ifndef _R819XU_PHYREG_H -#define _R819XU_PHYREG_H - - -#define RF_DATA 0x1d4 // FW will write RF data in the register. - -//Register //duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF -//page 1 -#define rPMAC_Reset 0x100 -#define rPMAC_TxStart 0x104 -#define rPMAC_TxLegacySIG 0x108 -#define rPMAC_TxHTSIG1 0x10c -#define rPMAC_TxHTSIG2 0x110 -#define rPMAC_PHYDebug 0x114 -#define rPMAC_TxPacketNum 0x118 -#define rPMAC_TxIdle 0x11c -#define rPMAC_TxMACHeader0 0x120 -#define rPMAC_TxMACHeader1 0x124 -#define rPMAC_TxMACHeader2 0x128 -#define rPMAC_TxMACHeader3 0x12c -#define rPMAC_TxMACHeader4 0x130 -#define rPMAC_TxMACHeader5 0x134 -#define rPMAC_TxDataType 0x138 -#define rPMAC_TxRandomSeed 0x13c -#define rPMAC_CCKPLCPPreamble 0x140 -#define rPMAC_CCKPLCPHeader 0x144 -#define rPMAC_CCKCRC16 0x148 -#define rPMAC_OFDMRxCRC32OK 0x170 -#define rPMAC_OFDMRxCRC32Er 0x174 -#define rPMAC_OFDMRxParityEr 0x178 -#define rPMAC_OFDMRxCRC8Er 0x17c -#define rPMAC_CCKCRxRC16Er 0x180 -#define rPMAC_CCKCRxRC32Er 0x184 -#define rPMAC_CCKCRxRC32OK 0x188 -#define rPMAC_TxStatus 0x18c - -//page8 -#define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC -#define rFPGA0_TxInfo 0x804 -#define rFPGA0_PSDFunction 0x808 -#define rFPGA0_TxGainStage 0x80c -#define rFPGA0_RFTiming1 0x810 -#define rFPGA0_RFTiming2 0x814 -//#define rFPGA0_XC_RFTiming 0x818 -//#define rFPGA0_XD_RFTiming 0x81c -#define rFPGA0_XA_HSSIParameter1 0x820 -#define rFPGA0_XA_HSSIParameter2 0x824 -#define rFPGA0_XB_HSSIParameter1 0x828 -#define rFPGA0_XB_HSSIParameter2 0x82c -#define rFPGA0_XC_HSSIParameter1 0x830 -#define rFPGA0_XC_HSSIParameter2 0x834 -#define rFPGA0_XD_HSSIParameter1 0x838 -#define rFPGA0_XD_HSSIParameter2 0x83c -#define rFPGA0_XA_LSSIParameter 0x840 -#define rFPGA0_XB_LSSIParameter 0x844 -#define rFPGA0_XC_LSSIParameter 0x848 -#define rFPGA0_XD_LSSIParameter 0x84c -#define rFPGA0_RFWakeUpParameter 0x850 -#define rFPGA0_RFSleepUpParameter 0x854 -#define rFPGA0_XAB_SwitchControl 0x858 -#define rFPGA0_XCD_SwitchControl 0x85c -#define rFPGA0_XA_RFInterfaceOE 0x860 -#define rFPGA0_XB_RFInterfaceOE 0x864 -#define rFPGA0_XC_RFInterfaceOE 0x868 -#define rFPGA0_XD_RFInterfaceOE 0x86c -#define rFPGA0_XAB_RFInterfaceSW 0x870 -#define rFPGA0_XCD_RFInterfaceSW 0x874 -#define rFPGA0_XAB_RFParameter 0x878 -#define rFPGA0_XCD_RFParameter 0x87c -#define rFPGA0_AnalogParameter1 0x880 -#define rFPGA0_AnalogParameter2 0x884 -#define rFPGA0_AnalogParameter3 0x888 -#define rFPGA0_AnalogParameter4 0x88c -#define rFPGA0_XA_LSSIReadBack 0x8a0 -#define rFPGA0_XB_LSSIReadBack 0x8a4 -#define rFPGA0_XC_LSSIReadBack 0x8a8 -#define rFPGA0_XD_LSSIReadBack 0x8ac -#define rFPGA0_PSDReport 0x8b4 -#define rFPGA0_XAB_RFInterfaceRB 0x8e0 -#define rFPGA0_XCD_RFInterfaceRB 0x8e4 - -//page 9 -#define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC -#define rFPGA1_TxBlock 0x904 -#define rFPGA1_DebugSelect 0x908 -#define rFPGA1_TxInfo 0x90c - -//page a -#define rCCK0_System 0xa00 -#define rCCK0_AFESetting 0xa04 -#define rCCK0_CCA 0xa08 -#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level -#define rCCK0_RxAGC2 0xa10 //AGC & DAGC -#define rCCK0_RxHP 0xa14 -#define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold -#define rCCK0_DSPParameter2 0xa1c //SQ threshold -#define rCCK0_TxFilter1 0xa20 -#define rCCK0_TxFilter2 0xa24 -#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3 -#define rCCK0_FalseAlarmReport 0xa2c //0xa2d -#define rCCK0_TRSSIReport 0xa50 -#define rCCK0_RxReport 0xa54 //0xa57 -#define rCCK0_FACounterLower 0xa5c //0xa5b -#define rCCK0_FACounterUpper 0xa58 //0xa5c - -//page c -#define rOFDM0_LSTF 0xc00 -#define rOFDM0_TRxPathEnable 0xc04 -#define rOFDM0_TRMuxPar 0xc08 -#define rOFDM0_TRSWIsolation 0xc0c -#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter -#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix -#define rOFDM0_XBRxAFE 0xc18 -#define rOFDM0_XBRxIQImbalance 0xc1c -#define rOFDM0_XCRxAFE 0xc20 -#define rOFDM0_XCRxIQImbalance 0xc24 -#define rOFDM0_XDRxAFE 0xc28 -#define rOFDM0_XDRxIQImbalance 0xc2c -#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD -#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync. -#define rOFDM0_RxDetector3 0xc38 //Frame Sync. -#define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI -#define rOFDM0_RxDSP 0xc40 //Rx Sync Path -#define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC -#define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold -#define rOFDM0_ECCAThreshold 0xc4c // energy CCA -#define rOFDM0_XAAGCCore1 0xc50 -#define rOFDM0_XAAGCCore2 0xc54 -#define rOFDM0_XBAGCCore1 0xc58 -#define rOFDM0_XBAGCCore2 0xc5c -#define rOFDM0_XCAGCCore1 0xc60 -#define rOFDM0_XCAGCCore2 0xc64 -#define rOFDM0_XDAGCCore1 0xc68 -#define rOFDM0_XDAGCCore2 0xc6c -#define rOFDM0_AGCParameter1 0xc70 -#define rOFDM0_AGCParameter2 0xc74 -#define rOFDM0_AGCRSSITable 0xc78 -#define rOFDM0_HTSTFAGC 0xc7c -#define rOFDM0_XATxIQImbalance 0xc80 -#define rOFDM0_XATxAFE 0xc84 -#define rOFDM0_XBTxIQImbalance 0xc88 -#define rOFDM0_XBTxAFE 0xc8c -#define rOFDM0_XCTxIQImbalance 0xc90 -#define rOFDM0_XCTxAFE 0xc94 -#define rOFDM0_XDTxIQImbalance 0xc98 -#define rOFDM0_XDTxAFE 0xc9c -#define rOFDM0_RxHPParameter 0xce0 -#define rOFDM0_TxPseudoNoiseWgt 0xce4 -#define rOFDM0_FrameSync 0xcf0 -#define rOFDM0_DFSReport 0xcf4 -#define rOFDM0_TxCoeff1 0xca4 -#define rOFDM0_TxCoeff2 0xca8 -#define rOFDM0_TxCoeff3 0xcac -#define rOFDM0_TxCoeff4 0xcb0 -#define rOFDM0_TxCoeff5 0xcb4 -#define rOFDM0_TxCoeff6 0xcb8 - - -//page d -#define rOFDM1_LSTF 0xd00 -#define rOFDM1_TRxPathEnable 0xd04 -#define rOFDM1_CFO 0xd08 -#define rOFDM1_CSI1 0xd10 -#define rOFDM1_SBD 0xd14 -#define rOFDM1_CSI2 0xd18 -#define rOFDM1_CFOTracking 0xd2c -#define rOFDM1_TRxMesaure1 0xd34 -#define rOFDM1_IntfDet 0xd3c -#define rOFDM1_PseudoNoiseStateAB 0xd50 -#define rOFDM1_PseudoNoiseStateCD 0xd54 -#define rOFDM1_RxPseudoNoiseWgt 0xd58 -#define rOFDM_PHYCounter1 0xda0 //cca, parity fail -#define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail -#define rOFDM_PHYCounter3 0xda8 //MCS not support -#define rOFDM_ShortCFOAB 0xdac -#define rOFDM_ShortCFOCD 0xdb0 -#define rOFDM_LongCFOAB 0xdb4 -#define rOFDM_LongCFOCD 0xdb8 -#define rOFDM_TailCFOAB 0xdbc -#define rOFDM_TailCFOCD 0xdc0 -#define rOFDM_PWMeasure1 0xdc4 -#define rOFDM_PWMeasure2 0xdc8 -#define rOFDM_BWReport 0xdcc -#define rOFDM_AGCReport 0xdd0 -#define rOFDM_RxSNR 0xdd4 -#define rOFDM_RxEVMCSI 0xdd8 -#define rOFDM_SIGReport 0xddc - -//page e -#define rTxAGC_Rate18_06 0xe00 -#define rTxAGC_Rate54_24 0xe04 -#define rTxAGC_CCK_Mcs32 0xe08 -#define rTxAGC_Mcs03_Mcs00 0xe10 -#define rTxAGC_Mcs07_Mcs04 0xe14 -#define rTxAGC_Mcs11_Mcs08 0xe18 -#define rTxAGC_Mcs15_Mcs12 0xe1c - - -//RF -//Zebra1 -#define rZebra1_HSSIEnable 0x0 -#define rZebra1_TRxEnable1 0x1 -#define rZebra1_TRxEnable2 0x2 -#define rZebra1_AGC 0x4 -#define rZebra1_ChargePump 0x5 -#define rZebra1_Channel 0x7 -#define rZebra1_TxGain 0x8 -#define rZebra1_TxLPF 0x9 -#define rZebra1_RxLPF 0xb -#define rZebra1_RxHPFCorner 0xc - -//Zebra4 -#define rGlobalCtrl 0 -#define rRTL8256_TxLPF 19 -#define rRTL8256_RxLPF 11 - -//RTL8258 -#define rRTL8258_TxLPF 0x11 -#define rRTL8258_RxLPF 0x13 -#define rRTL8258_RSSILPF 0xa - -//Bit Mask -//page-1 -#define bBBResetB 0x100 -#define bGlobalResetB 0x200 -#define bOFDMTxStart 0x4 -#define bCCKTxStart 0x8 -#define bCRC32Debug 0x100 -#define bPMACLoopback 0x10 -#define bTxLSIG 0xffffff -#define bOFDMTxRate 0xf -#define bOFDMTxReserved 0x10 -#define bOFDMTxLength 0x1ffe0 -#define bOFDMTxParity 0x20000 -#define bTxHTSIG1 0xffffff -#define bTxHTMCSRate 0x7f -#define bTxHTBW 0x80 -#define bTxHTLength 0xffff00 -#define bTxHTSIG2 0xffffff -#define bTxHTSmoothing 0x1 -#define bTxHTSounding 0x2 -#define bTxHTReserved 0x4 -#define bTxHTAggreation 0x8 -#define bTxHTSTBC 0x30 -#define bTxHTAdvanceCoding 0x40 -#define bTxHTShortGI 0x80 -#define bTxHTNumberHT_LTF 0x300 -#define bTxHTCRC8 0x3fc00 -#define bCounterReset 0x10000 -#define bNumOfOFDMTx 0xffff -#define bNumOfCCKTx 0xffff0000 -#define bTxIdleInterval 0xffff -#define bOFDMService 0xffff0000 -#define bTxMACHeader 0xffffffff -#define bTxDataInit 0xff -#define bTxHTMode 0x100 -#define bTxDataType 0x30000 -#define bTxRandomSeed 0xffffffff -#define bCCKTxPreamble 0x1 -#define bCCKTxSFD 0xffff0000 -#define bCCKTxSIG 0xff -#define bCCKTxService 0xff00 -#define bCCKLengthExt 0x8000 -#define bCCKTxLength 0xffff0000 -#define bCCKTxCRC16 0xffff -#define bCCKTxStatus 0x1 -#define bOFDMTxStatus 0x2 - -//page-8 -#define bRFMOD 0x1 -#define bJapanMode 0x2 -#define bCCKTxSC 0x30 -#define bCCKEn 0x1000000 -#define bOFDMEn 0x2000000 -#define bOFDMRxADCPhase 0x10000 -#define bOFDMTxDACPhase 0x40000 -#define bXATxAGC 0x3f -#define bXBTxAGC 0xf00 -#define bXCTxAGC 0xf000 -#define bXDTxAGC 0xf0000 -#define bPAStart 0xf0000000 -#define bTRStart 0x00f00000 -#define bRFStart 0x0000f000 -#define bBBStart 0x000000f0 -#define bBBCCKStart 0x0000000f -#define bPAEnd 0xf //Reg0x814 -#define bTREnd 0x0f000000 -#define bRFEnd 0x000f0000 -#define bCCAMask 0x000000f0 //T2R -#define bR2RCCAMask 0x00000f00 -#define bHSSI_R2TDelay 0xf8000000 -#define bHSSI_T2RDelay 0xf80000 -#define bContTxHSSI 0x400 //chane gain at continue Tx -#define bIGFromCCK 0x200 -#define bAGCAddress 0x3f -#define bRxHPTx 0x7000 -#define bRxHPT2R 0x38000 -#define bRxHPCCKIni 0xc0000 -#define bAGCTxCode 0xc00000 -#define bAGCRxCode 0x300000 -#define b3WireDataLength 0x800 -#define b3WireAddressLength 0x400 -#define b3WireRFPowerDown 0x1 -//#define bHWSISelect 0x8 -#define b5GPAPEPolarity 0x40000000 -#define b2GPAPEPolarity 0x80000000 -#define bRFSW_TxDefaultAnt 0x3 -#define bRFSW_TxOptionAnt 0x30 -#define bRFSW_RxDefaultAnt 0x300 -#define bRFSW_RxOptionAnt 0x3000 -#define bRFSI_3WireData 0x1 -#define bRFSI_3WireClock 0x2 -#define bRFSI_3WireLoad 0x4 -#define bRFSI_3WireRW 0x8 -#define bRFSI_3Wire 0xf //3-wire total control -#define bRFSI_RFENV 0x10 -#define bRFSI_TRSW 0x20 -#define bRFSI_TRSWB 0x40 -#define bRFSI_ANTSW 0x100 -#define bRFSI_ANTSWB 0x200 -#define bRFSI_PAPE 0x400 -#define bRFSI_PAPE5G 0x800 -#define bBandSelect 0x1 -#define bHTSIG2_GI 0x80 -#define bHTSIG2_Smoothing 0x01 -#define bHTSIG2_Sounding 0x02 -#define bHTSIG2_Aggreaton 0x08 -#define bHTSIG2_STBC 0x30 -#define bHTSIG2_AdvCoding 0x40 -#define bHTSIG2_NumOfHTLTF 0x300 -#define bHTSIG2_CRC8 0x3fc -#define bHTSIG1_MCS 0x7f -#define bHTSIG1_BandWidth 0x80 -#define bHTSIG1_HTLength 0xffff -#define bLSIG_Rate 0xf -#define bLSIG_Reserved 0x10 -#define bLSIG_Length 0x1fffe -#define bLSIG_Parity 0x20 -#define bCCKRxPhase 0x4 -#define bLSSIReadAddress 0x3f000000 //LSSI "Read" Address -#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal -#define bLSSIReadBackData 0xfff -#define bLSSIReadOKFlag 0x1000 -#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz - -#define bRegulator0Standby 0x1 -#define bRegulatorPLLStandby 0x2 -#define bRegulator1Standby 0x4 -#define bPLLPowerUp 0x8 -#define bDPLLPowerUp 0x10 -#define bDA10PowerUp 0x20 -#define bAD7PowerUp 0x200 -#define bDA6PowerUp 0x2000 -#define bXtalPowerUp 0x4000 -#define b40MDClkPowerUP 0x8000 -#define bDA6DebugMode 0x20000 -#define bDA6Swing 0x380000 -#define bADClkPhase 0x4000000 -#define b80MClkDelay 0x18000000 -#define bAFEWatchDogEnable 0x20000000 -#define bXtalCap 0x0f000000 -#define bIntDifClkEnable 0x400 -#define bExtSigClkEnable 0x800 -#define bBandgapMbiasPowerUp 0x10000 -#define bAD11SHGain 0xc0000 -#define bAD11InputRange 0x700000 -#define bAD11OPCurrent 0x3800000 -#define bIPathLoopback 0x4000000 -#define bQPathLoopback 0x8000000 -#define bAFELoopback 0x10000000 -#define bDA10Swing 0x7e0 -#define bDA10Reverse 0x800 -#define bDAClkSource 0x1000 -#define bAD7InputRange 0x6000 -#define bAD7Gain 0x38000 -#define bAD7OutputCMMode 0x40000 -#define bAD7InputCMMode 0x380000 -#define bAD7Current 0xc00000 -#define bRegulatorAdjust 0x7000000 -#define bAD11PowerUpAtTx 0x1 -#define bDA10PSAtTx 0x10 -#define bAD11PowerUpAtRx 0x100 -#define bDA10PSAtRx 0x1000 - -#define bCCKRxAGCFormat 0x200 - -#define bPSDFFTSamplepPoint 0xc000 -#define bPSDAverageNum 0x3000 -#define bIQPathControl 0xc00 -#define bPSDFreq 0x3ff -#define bPSDAntennaPath 0x30 -#define bPSDIQSwitch 0x40 -#define bPSDRxTrigger 0x400000 -#define bPSDTxTrigger 0x80000000 -#define bPSDSineToneScale 0x7f000000 -#define bPSDReport 0xffff - -//page-9 -#define bOFDMTxSC 0x30000000 -#define bCCKTxOn 0x1 -#define bOFDMTxOn 0x2 -#define bDebugPage 0xfff //reset debug page and also HWord, LWord -#define bDebugItem 0xff //reset debug page and LWord -#define bAntL 0x10 -#define bAntNonHT 0x100 -#define bAntHT1 0x1000 -#define bAntHT2 0x10000 -#define bAntHT1S1 0x100000 -#define bAntNonHTS1 0x1000000 - -//page-a -#define bCCKBBMode 0x3 -#define bCCKTxPowerSaving 0x80 -#define bCCKRxPowerSaving 0x40 -#define bCCKSideBand 0x10 -#define bCCKScramble 0x8 -#define bCCKAntDiversity 0x8000 -#define bCCKCarrierRecovery 0x4000 -#define bCCKTxRate 0x3000 -#define bCCKDCCancel 0x0800 -#define bCCKISICancel 0x0400 -#define bCCKMatchFilter 0x0200 -#define bCCKEqualizer 0x0100 -#define bCCKPreambleDetect 0x800000 -#define bCCKFastFalseCCA 0x400000 -#define bCCKChEstStart 0x300000 -#define bCCKCCACount 0x080000 -#define bCCKcs_lim 0x070000 -#define bCCKBistMode 0x80000000 -#define bCCKCCAMask 0x40000000 -#define bCCKTxDACPhase 0x4 -#define bCCKRxADCPhase 0x20000000 //r_rx_clk -#define bCCKr_cp_mode0 0x0100 -#define bCCKTxDCOffset 0xf0 -#define bCCKRxDCOffset 0xf -#define bCCKCCAMode 0xc000 -#define bCCKFalseCS_lim 0x3f00 -#define bCCKCS_ratio 0xc00000 -#define bCCKCorgBit_sel 0x300000 -#define bCCKPD_lim 0x0f0000 -#define bCCKNewCCA 0x80000000 -#define bCCKRxHPofIG 0x8000 -#define bCCKRxIG 0x7f00 -#define bCCKLNAPolarity 0x800000 -#define bCCKRx1stGain 0x7f0000 -#define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity -#define bCCKRxAGCSatLevel 0x1f000000 -#define bCCKRxAGCSatCount 0xe0 -#define bCCKRxRFSettle 0x1f //AGCsamp_dly -#define bCCKFixedRxAGC 0x8000 -//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824 -#define bCCKAntennaPolarity 0x2000 -#define bCCKTxFilterType 0x0c00 -#define bCCKRxAGCReportType 0x0300 -#define bCCKRxDAGCEn 0x80000000 -#define bCCKRxDAGCPeriod 0x20000000 -#define bCCKRxDAGCSatLevel 0x1f000000 -#define bCCKTimingRecovery 0x800000 -#define bCCKTxC0 0x3f0000 -#define bCCKTxC1 0x3f000000 -#define bCCKTxC2 0x3f -#define bCCKTxC3 0x3f00 -#define bCCKTxC4 0x3f0000 -#define bCCKTxC5 0x3f000000 -#define bCCKTxC6 0x3f -#define bCCKTxC7 0x3f00 -#define bCCKDebugPort 0xff0000 -#define bCCKDACDebug 0x0f000000 -#define bCCKFalseAlarmEnable 0x8000 -#define bCCKFalseAlarmRead 0x4000 -#define bCCKTRSSI 0x7f -#define bCCKRxAGCReport 0xfe -#define bCCKRxReport_AntSel 0x80000000 -#define bCCKRxReport_MFOff 0x40000000 -#define bCCKRxRxReport_SQLoss 0x20000000 -#define bCCKRxReport_Pktloss 0x10000000 -#define bCCKRxReport_Lockedbit 0x08000000 -#define bCCKRxReport_RateError 0x04000000 -#define bCCKRxReport_RxRate 0x03000000 -#define bCCKRxFACounterLower 0xff -#define bCCKRxFACounterUpper 0xff000000 -#define bCCKRxHPAGCStart 0xe000 -#define bCCKRxHPAGCFinal 0x1c00 - -#define bCCKRxFalseAlarmEnable 0x8000 -#define bCCKFACounterFreeze 0x4000 - -#define bCCKTxPathSel 0x10000000 -#define bCCKDefaultRxPath 0xc000000 -#define bCCKOptionRxPath 0x3000000 - -//page c -#define bNumOfSTF 0x3 -#define bShift_L 0xc0 -#define bGI_TH 0xc -#define bRxPathA 0x1 -#define bRxPathB 0x2 -#define bRxPathC 0x4 -#define bRxPathD 0x8 -#define bTxPathA 0x1 -#define bTxPathB 0x2 -#define bTxPathC 0x4 -#define bTxPathD 0x8 -#define bTRSSIFreq 0x200 -#define bADCBackoff 0x3000 -#define bDFIRBackoff 0xc000 -#define bTRSSILatchPhase 0x10000 -#define bRxIDCOffset 0xff -#define bRxQDCOffset 0xff00 -#define bRxDFIRMode 0x1800000 -#define bRxDCNFType 0xe000000 -#define bRXIQImb_A 0x3ff -#define bRXIQImb_B 0xfc00 -#define bRXIQImb_C 0x3f0000 -#define bRXIQImb_D 0xffc00000 -#define bDC_dc_Notch 0x60000 -#define bRxNBINotch 0x1f000000 -#define bPD_TH 0xf -#define bPD_TH_Opt2 0xc000 -#define bPWED_TH 0x700 -#define bIfMF_Win_L 0x800 -#define bPD_Option 0x1000 -#define bMF_Win_L 0xe000 -#define bBW_Search_L 0x30000 -#define bwin_enh_L 0xc0000 -#define bBW_TH 0x700000 -#define bED_TH2 0x3800000 -#define bBW_option 0x4000000 -#define bRatio_TH 0x18000000 -#define bWindow_L 0xe0000000 -#define bSBD_Option 0x1 -#define bFrame_TH 0x1c -#define bFS_Option 0x60 -#define bDC_Slope_check 0x80 -#define bFGuard_Counter_DC_L 0xe00 -#define bFrame_Weight_Short 0x7000 -#define bSub_Tune 0xe00000 -#define bFrame_DC_Length 0xe000000 -#define bSBD_start_offset 0x30000000 -#define bFrame_TH_2 0x7 -#define bFrame_GI2_TH 0x38 -#define bGI2_Sync_en 0x40 -#define bSarch_Short_Early 0x300 -#define bSarch_Short_Late 0xc00 -#define bSarch_GI2_Late 0x70000 -#define bCFOAntSum 0x1 -#define bCFOAcc 0x2 -#define bCFOStartOffset 0xc -#define bCFOLookBack 0x70 -#define bCFOSumWeight 0x80 -#define bDAGCEnable 0x10000 -#define bTXIQImb_A 0x3ff -#define bTXIQImb_B 0xfc00 -#define bTXIQImb_C 0x3f0000 -#define bTXIQImb_D 0xffc00000 -#define bTxIDCOffset 0xff -#define bTxQDCOffset 0xff00 -#define bTxDFIRMode 0x10000 -#define bTxPesudoNoiseOn 0x4000000 -#define bTxPesudoNoise_A 0xff -#define bTxPesudoNoise_B 0xff00 -#define bTxPesudoNoise_C 0xff0000 -#define bTxPesudoNoise_D 0xff000000 -#define bCCADropOption 0x20000 -#define bCCADropThres 0xfff00000 -#define bEDCCA_H 0xf -#define bEDCCA_L 0xf0 -#define bLambda_ED 0x300 -#define bRxInitialGain 0x7f -#define bRxAntDivEn 0x80 -#define bRxAGCAddressForLNA 0x7f00 -#define bRxHighPowerFlow 0x8000 -#define bRxAGCFreezeThres 0xc0000 -#define bRxFreezeStep_AGC1 0x300000 -#define bRxFreezeStep_AGC2 0xc00000 -#define bRxFreezeStep_AGC3 0x3000000 -#define bRxFreezeStep_AGC0 0xc000000 -#define bRxRssi_Cmp_En 0x10000000 -#define bRxQuickAGCEn 0x20000000 -#define bRxAGCFreezeThresMode 0x40000000 -#define bRxOverFlowCheckType 0x80000000 -#define bRxAGCShift 0x7f -#define bTRSW_Tri_Only 0x80 -#define bPowerThres 0x300 -#define bRxAGCEn 0x1 -#define bRxAGCTogetherEn 0x2 -#define bRxAGCMin 0x4 -#define bRxHP_Ini 0x7 -#define bRxHP_TRLNA 0x70 -#define bRxHP_RSSI 0x700 -#define bRxHP_BBP1 0x7000 -#define bRxHP_BBP2 0x70000 -#define bRxHP_BBP3 0x700000 -#define bRSSI_H 0x7f0000 //the threshold for high power -#define bRSSI_Gen 0x7f000000 //the threshold for ant diversity -#define bRxSettle_TRSW 0x7 -#define bRxSettle_LNA 0x38 -#define bRxSettle_RSSI 0x1c0 -#define bRxSettle_BBP 0xe00 -#define bRxSettle_RxHP 0x7000 -#define bRxSettle_AntSW_RSSI 0x38000 -#define bRxSettle_AntSW 0xc0000 -#define bRxProcessTime_DAGC 0x300000 -#define bRxSettle_HSSI 0x400000 -#define bRxProcessTime_BBPPW 0x800000 -#define bRxAntennaPowerShift 0x3000000 -#define bRSSITableSelect 0xc000000 -#define bRxHP_Final 0x7000000 -#define bRxHTSettle_BBP 0x7 -#define bRxHTSettle_HSSI 0x8 -#define bRxHTSettle_RxHP 0x70 -#define bRxHTSettle_BBPPW 0x80 -#define bRxHTSettle_Idle 0x300 -#define bRxHTSettle_Reserved 0x1c00 -#define bRxHTRxHPEn 0x8000 -#define bRxHTAGCFreezeThres 0x30000 -#define bRxHTAGCTogetherEn 0x40000 -#define bRxHTAGCMin 0x80000 -#define bRxHTAGCEn 0x100000 -#define bRxHTDAGCEn 0x200000 -#define bRxHTRxHP_BBP 0x1c00000 -#define bRxHTRxHP_Final 0xe0000000 -#define bRxPWRatioTH 0x3 -#define bRxPWRatioEn 0x4 -#define bRxMFHold 0x3800 -#define bRxPD_Delay_TH1 0x38 -#define bRxPD_Delay_TH2 0x1c0 -#define bRxPD_DC_COUNT_MAX 0x600 -//#define bRxMF_Hold 0x3800 -#define bRxPD_Delay_TH 0x8000 -#define bRxProcess_Delay 0xf0000 -#define bRxSearchrange_GI2_Early 0x700000 -#define bRxFrame_Guard_Counter_L 0x3800000 -#define bRxSGI_Guard_L 0xc000000 -#define bRxSGI_Search_L 0x30000000 -#define bRxSGI_TH 0xc0000000 -#define bDFSCnt0 0xff -#define bDFSCnt1 0xff00 -#define bDFSFlag 0xf0000 - -#define bMFWeightSum 0x300000 -#define bMinIdxTH 0x7f000000 - -#define bDAFormat 0x40000 - -#define bTxChEmuEnable 0x01000000 - -#define bTRSWIsolation_A 0x7f -#define bTRSWIsolation_B 0x7f00 -#define bTRSWIsolation_C 0x7f0000 -#define bTRSWIsolation_D 0x7f000000 - -#define bExtLNAGain 0x7c00 - -//page d -#define bSTBCEn 0x4 -#define bAntennaMapping 0x10 -#define bNss 0x20 -#define bCFOAntSumD 0x200 -#define bPHYCounterReset 0x8000000 -#define bCFOReportGet 0x4000000 -#define bOFDMContinueTx 0x10000000 -#define bOFDMSingleCarrier 0x20000000 -#define bOFDMSingleTone 0x40000000 -//#define bRxPath1 0x01 -//#define bRxPath2 0x02 -//#define bRxPath3 0x04 -//#define bRxPath4 0x08 -//#define bTxPath1 0x10 -//#define bTxPath2 0x20 -#define bHTDetect 0x100 -#define bCFOEn 0x10000 -#define bCFOValue 0xfff00000 -#define bSigTone_Re 0x3f -#define bSigTone_Im 0x7f00 -#define bCounter_CCA 0xffff -#define bCounter_ParityFail 0xffff0000 -#define bCounter_RateIllegal 0xffff -#define bCounter_CRC8Fail 0xffff0000 -#define bCounter_MCSNoSupport 0xffff -#define bCounter_FastSync 0xffff -#define bShortCFO 0xfff -#define bShortCFOTLength 12 //total -#define bShortCFOFLength 11 //fraction -#define bLongCFO 0x7ff -#define bLongCFOTLength 11 -#define bLongCFOFLength 11 -#define bTailCFO 0x1fff -#define bTailCFOTLength 13 -#define bTailCFOFLength 12 - -#define bmax_en_pwdB 0xffff -#define bCC_power_dB 0xffff0000 -#define bnoise_pwdB 0xffff -#define bPowerMeasTLength 10 -#define bPowerMeasFLength 3 -#define bRx_HT_BW 0x1 -#define bRxSC 0x6 -#define bRx_HT 0x8 - -#define bNB_intf_det_on 0x1 -#define bIntf_win_len_cfg 0x30 -#define bNB_Intf_TH_cfg 0x1c0 - -#define bRFGain 0x3f -#define bTableSel 0x40 -#define bTRSW 0x80 - -#define bRxSNR_A 0xff -#define bRxSNR_B 0xff00 -#define bRxSNR_C 0xff0000 -#define bRxSNR_D 0xff000000 -#define bSNREVMTLength 8 -#define bSNREVMFLength 1 - -#define bCSI1st 0xff -#define bCSI2nd 0xff00 -#define bRxEVM1st 0xff0000 -#define bRxEVM2nd 0xff000000 - -#define bSIGEVM 0xff -#define bPWDB 0xff00 -#define bSGIEN 0x10000 - -#define bSFactorQAM1 0xf -#define bSFactorQAM2 0xf0 -#define bSFactorQAM3 0xf00 -#define bSFactorQAM4 0xf000 -#define bSFactorQAM5 0xf0000 -#define bSFactorQAM6 0xf0000 -#define bSFactorQAM7 0xf00000 -#define bSFactorQAM8 0xf000000 -#define bSFactorQAM9 0xf0000000 -#define bCSIScheme 0x100000 - -#define bNoiseLvlTopSet 0x3 -#define bChSmooth 0x4 -#define bChSmoothCfg1 0x38 -#define bChSmoothCfg2 0x1c0 -#define bChSmoothCfg3 0xe00 -#define bChSmoothCfg4 0x7000 -#define bMRCMode 0x800000 -#define bTHEVMCfg 0x7000000 - -#define bLoopFitType 0x1 -#define bUpdCFO 0x40 -#define bUpdCFOOffData 0x80 -#define bAdvUpdCFO 0x100 -#define bAdvTimeCtrl 0x800 -#define bUpdClko 0x1000 -#define bFC 0x6000 -#define bTrackingMode 0x8000 -#define bPhCmpEnable 0x10000 -#define bUpdClkoLTF 0x20000 -#define bComChCFO 0x40000 -#define bCSIEstiMode 0x80000 -#define bAdvUpdEqz 0x100000 -#define bUChCfg 0x7000000 -#define bUpdEqz 0x8000000 - -//page e -#define bTxAGCRate18_06 0x7f7f7f7f -#define bTxAGCRate54_24 0x7f7f7f7f -#define bTxAGCRateMCS32 0x7f -#define bTxAGCRateCCK 0x7f00 -#define bTxAGCRateMCS3_MCS0 0x7f7f7f7f -#define bTxAGCRateMCS7_MCS4 0x7f7f7f7f -#define bTxAGCRateMCS11_MCS8 0x7f7f7f7f -#define bTxAGCRateMCS15_MCS12 0x7f7f7f7f - - -//Rx Pseduo noise -#define bRxPesudoNoiseOn 0x20000000 -#define bRxPesudoNoise_A 0xff -#define bRxPesudoNoise_B 0xff00 -#define bRxPesudoNoise_C 0xff0000 -#define bRxPesudoNoise_D 0xff000000 -#define bPesudoNoiseState_A 0xffff -#define bPesudoNoiseState_B 0xffff0000 -#define bPesudoNoiseState_C 0xffff -#define bPesudoNoiseState_D 0xffff0000 - -//RF -//Zebra1 -#define bZebra1_HSSIEnable 0x8 -#define bZebra1_TRxControl 0xc00 -#define bZebra1_TRxGainSetting 0x07f -#define bZebra1_RxCorner 0xc00 -#define bZebra1_TxChargePump 0x38 -#define bZebra1_RxChargePump 0x7 -#define bZebra1_ChannelNum 0xf80 -#define bZebra1_TxLPFBW 0x400 -#define bZebra1_RxLPFBW 0x600 - -//Zebra4 -#define bRTL8256RegModeCtrl1 0x100 -#define bRTL8256RegModeCtrl0 0x40 -#define bRTL8256_TxLPFBW 0x18 -#define bRTL8256_RxLPFBW 0x600 - -//RTL8258 -#define bRTL8258_TxLPFBW 0xc -#define bRTL8258_RxLPFBW 0xc00 -#define bRTL8258_RSSILPFBW 0xc0 - -//byte endable for sb_write -#define bByte0 0x1 -#define bByte1 0x2 -#define bByte2 0x4 -#define bByte3 0x8 -#define bWord0 0x3 -#define bWord1 0xc -#define bDWord 0xf - -//for PutRegsetting & GetRegSetting BitMask -#define bMaskByte0 0xff -#define bMaskByte1 0xff00 -#define bMaskByte2 0xff0000 -#define bMaskByte3 0xff000000 -#define bMaskHWord 0xffff0000 -#define bMaskLWord 0x0000ffff -#define bMaskDWord 0xffffffff - -//for PutRFRegsetting & GetRFRegSetting BitMask -#define bMask12Bits 0xfff - -#define bEnable 0x1 -#define bDisable 0x0 - -#define LeftAntenna 0x0 -#define RightAntenna 0x1 - -#define tCheckTxStatus 500 //500ms -#define tUpdateRxCounter 100 //100ms - -#define rateCCK 0 -#define rateOFDM 1 -#define rateHT 2 - -//define Register-End -#define bPMAC_End 0x1ff -#define bFPGAPHY0_End 0x8ff -#define bFPGAPHY1_End 0x9ff -#define bCCKPHY0_End 0xaff -#define bOFDMPHY0_End 0xcff -#define bOFDMPHY1_End 0xdff - -//define max debug item in each debug page -//#define bMaxItem_FPGA_PHY0 0x9 -//#define bMaxItem_FPGA_PHY1 0x3 -//#define bMaxItem_PHY_11B 0x16 -//#define bMaxItem_OFDM_PHY0 0x29 -//#define bMaxItem_OFDM_PHY1 0x0 - -#define bPMACControl 0x0 -#define bWMACControl 0x1 -#define bWNICControl 0x2 - -#define PathA 0x0 -#define PathB 0x1 -#define PathC 0x2 -#define PathD 0x3 - -#define rRTL8256RxMixerPole 0xb -#define bZebraRxMixerPole 0x6 -#define rRTL8256TxBBOPBias 0x9 -#define bRTL8256TxBBOPBias 0x400 -#define rRTL8256TxBBBW 19 -#define bRTL8256TxBBBW 0x18 - -#endif //__INC_HAL8190PCIPHYREG_H |