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authorUlrich Hecht <uli+renesas@fpond.eu>2021-01-12 17:59:29 +0100
committerGeert Uytterhoeven <geert+renesas@glider.be>2021-01-14 12:06:16 +0100
commita5cda861ed57710837bc560a3c715160da710555 (patch)
tree41e7890554d6ec61e0fbbcb2176559d3f2e32c0a /drivers/pinctrl/renesas
parentb3761cd6e1565e3d20612f8f8499780625d80aa2 (diff)
pinctrl: renesas: r8a779a0: Add TPU pins, groups and functions
Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs on the R-Car R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20210112165929.31002-13-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/pinctrl/renesas')
-rw-r--r--drivers/pinctrl/renesas/pfc-r8a779a0.c44
1 files changed, 44 insertions, 0 deletions
diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c
index a85e2c750e41..2250ccd0470a 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779a0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c
@@ -2582,6 +2582,36 @@ static const unsigned int tmu_tclk4_mux[] = {
TCLK4_MARK,
};
+/* - TPU ------------------------------------------------------------------- */
+static const unsigned int tpu_to0_pins[] = {
+ /* TPU0TO0 */
+ RCAR_GP_PIN(2, 21),
+};
+static const unsigned int tpu_to0_mux[] = {
+ TPU0TO0_MARK,
+};
+static const unsigned int tpu_to1_pins[] = {
+ /* TPU0TO1 */
+ RCAR_GP_PIN(2, 22),
+};
+static const unsigned int tpu_to1_mux[] = {
+ TPU0TO1_MARK,
+};
+static const unsigned int tpu_to2_pins[] = {
+ /* TPU0TO2 */
+ RCAR_GP_PIN(3, 5),
+};
+static const unsigned int tpu_to2_mux[] = {
+ TPU0TO2_MARK,
+};
+static const unsigned int tpu_to3_pins[] = {
+ /* TPU0TO3 */
+ RCAR_GP_PIN(3, 6),
+};
+static const unsigned int tpu_to3_mux[] = {
+ TPU0TO3_MARK,
+};
+
static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(avb0_link),
SH_PFC_PIN_GROUP(avb0_magic),
@@ -2765,6 +2795,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(tmu_tclk2_b),
SH_PFC_PIN_GROUP(tmu_tclk3),
SH_PFC_PIN_GROUP(tmu_tclk4),
+
+ SH_PFC_PIN_GROUP(tpu_to0),
+ SH_PFC_PIN_GROUP(tpu_to1),
+ SH_PFC_PIN_GROUP(tpu_to2),
+ SH_PFC_PIN_GROUP(tpu_to3),
};
static const char * const avb0_groups[] = {
@@ -3077,6 +3112,13 @@ static const char * const tmu_groups[] = {
"tmu_tclk4",
};
+static const char * const tpu_groups[] = {
+ "tpu_to0",
+ "tpu_to1",
+ "tpu_to2",
+ "tpu_to3",
+};
+
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(avb0),
SH_PFC_FUNCTION(avb1),
@@ -3137,6 +3179,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(scif_clk),
SH_PFC_FUNCTION(tmu),
+
+ SH_PFC_FUNCTION(tpu),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {