diff options
| author | Thierry Reding <treding@nvidia.com> | 2015-08-06 14:20:31 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2015-08-13 17:05:28 +0200 |
| commit | 11cec15bf3fb498206ef63b1fa26c27689e02d0e (patch) | |
| tree | 330bd3eff26a1915e86b5e896cdee4db2c909896 /drivers/memory/tegra/tegra30.c | |
| parent | 4080e99b8341f81c4ed1e17d8ef44d171c473a1b (diff) | |
iommu/tegra-smmu: Parameterize number of TLB lines
The number of TLB lines was increased from 16 on Tegra30 to 32 on
Tegra114 and later. Parameterize the value so that the initial default
can be set accordingly.
On Tegra30, initializing the value to 32 would effectively disable the
TLB and hence cause massive latencies for memory accesses translated
through the SMMU. This is especially noticeable for isochronuous clients
such as display, whose FIFOs would continuously underrun.
Fixes: 891846516317 ("memory: Add NVIDIA Tegra memory controller support")
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/memory/tegra/tegra30.c')
| -rw-r--r-- | drivers/memory/tegra/tegra30.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/memory/tegra/tegra30.c b/drivers/memory/tegra/tegra30.c index 3cb30b69d95b..7e0694d80edb 100644 --- a/drivers/memory/tegra/tegra30.c +++ b/drivers/memory/tegra/tegra30.c @@ -941,6 +941,7 @@ static const struct tegra_smmu_soc tegra30_smmu_soc = { .num_swgroups = ARRAY_SIZE(tegra30_swgroups), .supports_round_robin_arbitration = false, .supports_request_limit = false, + .num_tlb_lines = 16, .num_asids = 4, }; |