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authorBrendan Higgins <brendanhiggins@google.com>2017-06-02 18:29:49 -0700
committerMarc Zyngier <marc.zyngier@arm.com>2017-06-22 14:15:00 +0100
commitf48e699ddf7056f83bb8e2dbe3c2ae8d1ff1a31a (patch)
treeacdac0e97e8286bee1ebdb30e21aa8f8e9013a1e /drivers/irqchip/Makefile
parent0a56f9eebe6320980b68c60c852436cbf2a14b61 (diff)
irqchip/aspeed-i2c-ic: Add I2C IRQ controller for Aspeed
The Aspeed 24XX/25XX chips share a single hardware interrupt across 14 separate I2C busses. This adds a dummy irqchip which maps the single hardware interrupt to software interrupts for each of the busses. Signed-off-by: Brendan Higgins <brendanhiggins@google.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'drivers/irqchip/Makefile')
-rw-r--r--drivers/irqchip/Makefile2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index b64c59b838a0..e067f9839b33 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -73,6 +73,6 @@ obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o
obj-$(CONFIG_MVEBU_PIC) += irq-mvebu-pic.o
obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o
obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o
-obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o
+obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o
obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o
obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o