diff options
| author | Leonard Crestez <leonard.crestez@nxp.com> | 2019-11-22 23:45:03 +0200 |
|---|---|---|
| committer | Chanwoo Choi <cw00.choi@samsung.com> | 2019-12-30 09:59:05 +0900 |
| commit | 5af744ebae856a50e8b5e208a5acf28713a4ce98 (patch) | |
| tree | 26f1fc739896b4503768c1062756ce219e786034 /drivers/devfreq/Kconfig | |
| parent | c49a5d0968690a08378fd14371678c3479f269aa (diff) | |
PM / devfreq: Add dynamic scaling for imx8m ddr controller
Add driver for dynamic scaling the DDR Controller on imx8m chips. Actual
frequency switching is implemented inside TF-A, this driver wraps the
SMC calls and synchronizes the clk tree.
The DRAM clocks on imx8m have the following structure (abridged):
+----------+ |\ +------+
| dram_pll |-------|M| dram_core | |
+----------+ |U|---------->| D |
/--|X| | D |
dram_alt_root | |/ | R |
| | C |
+---------+ | |
|FIX DIV/4| | |
+---------+ | |
composite: | | |
+----------+ | | |
| dram_alt |----/ | |
+----------+ | |
| dram_apb |-------------------->| |
+----------+ +------+
The dram_pll is used for higher rates and dram_alt is used for lower
rates. The dram_alt and dram_apb clocks are "imx composite" and their
parent can also be modified.
This driver will prepare/enable the new parents ahead of switching (so
that the expected roots are enabled) and afterwards it will call
clk_set_parent to ensure the parents in clock framework are up-to-date.
The driver relies on dram_pll dram_alt and dram_apb being marked with
CLK_GET_RATE_NOCACHE for rate updates.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
[cw00.choi: Edit the COMPILE_TEST module dependency in Kconfig]
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Diffstat (limited to 'drivers/devfreq/Kconfig')
| -rw-r--r-- | drivers/devfreq/Kconfig | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig index ca45d57ad947..8485f948caeb 100644 --- a/drivers/devfreq/Kconfig +++ b/drivers/devfreq/Kconfig @@ -91,6 +91,16 @@ config ARM_EXYNOS_BUS_DEVFREQ and adjusts the operating frequencies and voltages with OPP support. This does not yet operate with optimal voltages. +config ARM_IMX8M_DDRC_DEVFREQ + tristate "i.MX8M DDRC DEVFREQ Driver" + depends on (ARCH_MXC && HAVE_ARM_SMCCC) || \ + (COMPILE_TEST && HAVE_ARM_SMCCC) + select DEVFREQ_GOV_SIMPLE_ONDEMAND + select DEVFREQ_GOV_USERSPACE + help + This adds the DEVFREQ driver for the i.MX8M DDR Controller. It allows + adjusting DRAM frequency. + config ARM_TEGRA_DEVFREQ tristate "NVIDIA Tegra30/114/124/210 DEVFREQ Driver" depends on ARCH_TEGRA_3x_SOC || ARCH_TEGRA_114_SOC || \ |