diff options
| author | Thierry Reding <treding@nvidia.com> | 2015-03-26 17:43:56 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2015-04-10 16:04:20 +0200 |
| commit | 63cc5a4da1fafedee24d8f5af67c1dd9d08f95c7 (patch) | |
| tree | cd2e48fa02b4982784ad5cf7c09bd0eb90fc06c8 /drivers/clk/tegra/clk-tegra30.c | |
| parent | 699b477a0d3a5bc68034a1520a4337ea0a20f63b (diff) | |
clk: tegra: Model oscillator as clock
Currently the Tegra clock driver simplifies the clock tree somewhat by
taking advantage of the fact that clk_m runs at the same frequency as
the oscillator. While that's true on all currently supported SoCs, it
does not apply to Tegra210 anymore. On Tegra210 clk_m is typically
divided down from the oscillator frequency. To support that setup, add
a separate clock for the oscillator that both clk_m and pll_ref derive
from.
Modify the tegra_osc_clk_init() function to take an additional divider
parameter for clk_m. Existing SoCs always pass in 1, whereas Tegra210
will read the divider from a register in the clock & reset controller.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-tegra30.c')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra30.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 0659db79d1c5..4b26509fc218 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -1434,7 +1434,8 @@ static void __init tegra30_clock_init(struct device_node *np) return; if (tegra_osc_clk_init(clk_base, tegra30_clks, tegra30_input_freq, - ARRAY_SIZE(tegra30_input_freq), &input_freq, NULL) < 0) + ARRAY_SIZE(tegra30_input_freq), 1, &input_freq, + NULL) < 0) return; |