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authorTuomas Tynkkynen <ttynkkynen@nvidia.com>2015-05-13 17:58:36 +0300
committerThierry Reding <treding@nvidia.com>2015-07-16 09:32:44 +0200
commitd8d7a08fa82ff7c241c74c2461f342c5685dda27 (patch)
tree297830915eb9d7e0ec578bf80656324498d0dc33 /drivers/clk/tegra/Makefile
parent0c59d26770333cf605d9119a78dd6c1ebebc6a61 (diff)
clk: tegra: Add library for the DFLL clock source (open-loop mode)
Add shared code to support the Tegra DFLL clocksource in open-loop mode. This root clocksource is present on the Tegra124 SoCs. The DFLL is the intended primary clock source for the fast CPU cluster. This code is very closely based on a patch by Paul Walmsley from December (http://comments.gmane.org/gmane.linux.ports.tegra/15273), which in turn comes from the internal driver by originally created by Aleksandr Frid <afrid@nvidia.com>. Subsequent patches will add support for closed loop mode and drivers for the Tegra124 fast CPU cluster DFLL devices, which rely on this code. Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com> Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Michael Turquette <mturquette@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/Makefile')
-rw-r--r--drivers/clk/tegra/Makefile1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
index aec862ba7a17..ec2e5163e1ae 100644
--- a/drivers/clk/tegra/Makefile
+++ b/drivers/clk/tegra/Makefile
@@ -1,5 +1,6 @@
obj-y += clk.o
obj-y += clk-audio-sync.o
+obj-y += clk-dfll.o
obj-y += clk-divider.o
obj-y += clk-periph.o
obj-y += clk-periph-gate.o