diff options
| author | tianshuliang <tianshuliang@hisilicon.com> | 2018-03-05 15:01:31 +0800 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2018-03-12 15:56:40 +0800 |
| commit | 811f67cc16ec76c3953ca1b9d7c34e3f0c17f779 (patch) | |
| tree | 0039cb365be56dadac52263dc5f6bb7413e99495 /drivers/clk/hisilicon/clk.c | |
| parent | 80f8ce589517c478abdae07a758b37b362886cb2 (diff) | |
clk: hisilicon: add hisi phase clock support
Add a phase clock type for HiSilicon SoCs,which supports
clk_set_phase operation.
Signed-off-by: tianshuliang <tianshuliang@hisilicon.com>
Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'drivers/clk/hisilicon/clk.c')
| -rw-r--r-- | drivers/clk/hisilicon/clk.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/drivers/clk/hisilicon/clk.c b/drivers/clk/hisilicon/clk.c index b73c1dfae7f1..29046b8334c2 100644 --- a/drivers/clk/hisilicon/clk.c +++ b/drivers/clk/hisilicon/clk.c @@ -197,6 +197,30 @@ err: } EXPORT_SYMBOL_GPL(hisi_clk_register_mux); +int hisi_clk_register_phase(struct device *dev, + const struct hisi_phase_clock *clks, + int nums, struct hisi_clock_data *data) +{ + void __iomem *base = data->base; + struct clk *clk; + int i; + + for (i = 0; i < nums; i++) { + clk = clk_register_hisi_phase(dev, &clks[i], base, + &hisi_clk_lock); + if (IS_ERR(clk)) { + pr_err("%s: failed to register clock %s\n", __func__, + clks[i].name); + return PTR_ERR(clk); + } + + data->clk_data.clks[clks[i].id] = clk; + } + + return 0; +} +EXPORT_SYMBOL_GPL(hisi_clk_register_phase); + int hisi_clk_register_divider(const struct hisi_divider_clock *clks, int nums, struct hisi_clock_data *data) { |