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| author | Michal Simek <michal.simek@xilinx.com> | 2014-04-07 13:05:00 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2014-04-07 13:45:21 +0200 |
| commit | c24cf712ac53ae8a7bedceb1c967da1667431d8e (patch) | |
| tree | a2f148f99936397d8b5edf75af99e89c681ee14c /arch/microblaze/Kconfig.platform | |
| parent | ed85ed697d8d66f4b3284d7a8a3dc7002c966178 (diff) | |
microblaze: Remove platform folder
There is no reason to use platform folder structure now.
Everything is OF driven.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/microblaze/Kconfig.platform')
| -rw-r--r-- | arch/microblaze/Kconfig.platform | 69 |
1 files changed, 69 insertions, 0 deletions
diff --git a/arch/microblaze/Kconfig.platform b/arch/microblaze/Kconfig.platform new file mode 100644 index 000000000000..1b3d8c849101 --- /dev/null +++ b/arch/microblaze/Kconfig.platform @@ -0,0 +1,69 @@ +# For a description of the syntax of this configuration file, +# see Documentation/kbuild/kconfig-language.txt. +# +# Platform selection Kconfig menu for MicroBlaze targets +# + +menu "Platform options" + +config OPT_LIB_FUNCTION + bool "Optimalized lib function" + default y + help + Allows turn on optimalized library function (memcpy and memmove). + They are optimized by using word alignment. This will work + fine if both source and destination are aligned on the same + boundary. However, if they are aligned on different boundaries + shifts will be necessary. This might result in bad performance + on MicroBlaze systems without a barrel shifter. + +config OPT_LIB_ASM + bool "Optimalized lib function ASM" + depends on OPT_LIB_FUNCTION && (XILINX_MICROBLAZE0_USE_BARREL = 1) + default n + help + Allows turn on optimalized library function (memcpy and memmove). + Function are written in asm code. + +# Definitions for MICROBLAZE0 +comment "Definitions for MICROBLAZE0" + +config KERNEL_BASE_ADDR + hex "Physical address where Linux Kernel is" + default "0x90000000" + help + BASE Address for kernel + +config XILINX_MICROBLAZE0_FAMILY + string "Targeted FPGA family" + default "virtex5" + +config XILINX_MICROBLAZE0_USE_MSR_INSTR + int "USE_MSR_INSTR range (0:1)" + default 0 + +config XILINX_MICROBLAZE0_USE_PCMP_INSTR + int "USE_PCMP_INSTR range (0:1)" + default 0 + +config XILINX_MICROBLAZE0_USE_BARREL + int "USE_BARREL range (0:1)" + default 0 + +config XILINX_MICROBLAZE0_USE_DIV + int "USE_DIV range (0:1)" + default 0 + +config XILINX_MICROBLAZE0_USE_HW_MUL + int "USE_HW_MUL values (0=NONE, 1=MUL32, 2=MUL64)" + default 0 + +config XILINX_MICROBLAZE0_USE_FPU + int "USE_FPU values (0=NONE, 1=BASIC, 2=EXTENDED)" + default 0 + +config XILINX_MICROBLAZE0_HW_VER + string "Core version number" + default 7.10.d + +endmenu |