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authorChen-Yu Tsai <wens@csie.org>2015-03-25 01:22:09 +0800
committerMaxime Ripard <maxime.ripard@free-electrons.com>2015-04-27 09:03:53 +0200
commit2186df37831a8bb259bbf2ae07356747a03d0b8d (patch)
tree485561918072205ed40fba360756878d6fbcc99e /arch/arm/boot
parentae3bdfe0efe0417b702e6501015375c44226ec23 (diff)
ARM: dts: sunxi: Update ahb clocks for sun5i and sun7i
The clock driver now supports a muxable ahb clock. Update the dtsi with the proper compatible and add the new parent clocks. This also adds the new pll6/4 output for pll6 on sun7i-a20. The output is not used on sun4/5i. Also use assigned-clocks to reparent ahb to pll6. We want ahb to have a stable, non-changing clock rate. cpu/axi clock rate changes as a result of newly added cpufreq support. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/sun5i.dtsi10
-rw-r--r--arch/arm/boot/dts/sun7i-a20.dtsi13
2 files changed, 18 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 96b20d646b3f..8c04f240f2e9 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -150,10 +150,16 @@
ahb: ahb@01c20054 {
#clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-ahb-clk";
+ compatible = "allwinner,sun5i-a13-ahb-clk";
reg = <0x01c20054 0x4>;
- clocks = <&axi>;
+ clocks = <&axi>, <&cpu>, <&pll6 1>;
clock-output-names = "ahb";
+ /*
+ * Use PLL6 as parent, instead of CPU/AXI
+ * which has rate changes due to cpufreq
+ */
+ assigned-clocks = <&ahb>;
+ assigned-clock-parents = <&pll6 1>;
};
apb0: apb0@01c20054 {
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index d4ba77202d7a..4163ade867cb 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -224,7 +224,8 @@
compatible = "allwinner,sun4i-a10-pll6-clk";
reg = <0x01c20028 0x4>;
clocks = <&osc24M>;
- clock-output-names = "pll6_sata", "pll6_other", "pll6";
+ clock-output-names = "pll6_sata", "pll6_other", "pll6",
+ "pll6_div_4";
};
pll8: clk@01c20040 {
@@ -253,10 +254,16 @@
ahb: ahb@01c20054 {
#clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-ahb-clk";
+ compatible = "allwinner,sun5i-a13-ahb-clk";
reg = <0x01c20054 0x4>;
- clocks = <&axi>;
+ clocks = <&axi>, <&pll6 3>, <&pll6 1>;
clock-output-names = "ahb";
+ /*
+ * Use PLL6 as parent, instead of CPU/AXI
+ * which has rate changes due to cpufreq
+ */
+ assigned-clocks = <&ahb>;
+ assigned-clock-parents = <&pll6 3>;
};
ahb_gates: clk@01c20060 {