diff options
| author | Gabriel FERNANDEZ <gabriel.fernandez@st.com> | 2014-08-25 16:44:00 +0200 |
|---|---|---|
| committer | Maxime Coquelin <maxime.coquelin@st.com> | 2014-10-31 09:59:10 +0100 |
| commit | 89e5c085748b0bc3333eb60b1a668f11f1ce99f4 (patch) | |
| tree | 66324faef43c752f97adbfde2cfcfe2ea34938a5 /arch/arm/boot/dts/stih407-clock.dtsi | |
| parent | 6e67a5105d5e89af245dadf6c4c0e5d15adc74a2 (diff) | |
ARM: STi: DT: STiH407: 407 DT Entry for clockgenA9
Patch adds DT entries for clockgen A9
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Diffstat (limited to 'arch/arm/boot/dts/stih407-clock.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/stih407-clock.dtsi | 55 |
1 files changed, 52 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi index 5f7a88d95879..a2667a1a0ac8 100644 --- a/arch/arm/boot/dts/stih407-clock.dtsi +++ b/arch/arm/boot/dts/stih407-clock.dtsi @@ -24,10 +24,59 @@ /* * ARM Peripheral clock for timers */ - arm_periph_clk: arm-periph-clk { + arm_periph_clk: clk-m-a9-periphs { #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <600000000>; + compatible = "fixed-factor-clock"; + + clocks = <&clk_m_a9>; + clock-div = <2>; + clock-mult = <1>; + }; + + /* + * A9 PLL. + */ + clockgen-a9@92b0000 { + compatible = "st,clkgen-c32"; + reg = <0x92b0000 0xffff>; + + clockgen_a9_pll: clockgen-a9-pll { + #clock-cells = <1>; + compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32"; + + clocks = <&clk_sysin>; + + clock-output-names = "clockgen-a9-pll-odf"; + }; + }; + + /* + * ARM CPU related clocks. + */ + clk_m_a9: clk-m-a9@92b0000 { + #clock-cells = <0>; + compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; + reg = <0x92b0000 0x10000>; + + clocks = <&clockgen_a9_pll 0>, + <&clockgen_a9_pll 0>, + <&clk_s_c0_flexgen 13>, + <&clk_m_a9_ext2f_div2>; + }; + + /* + * ARM Peripheral clock for timers + */ + clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + + clocks = <&clk_s_c0_flexgen 13>; + + clock-output-names = "clk-m-a9-ext2f-div2"; + + clock-div = <2>; + clock-mult = <1>; }; /* |