Implement extension cl_intel_device_side_avc_motion_estimation.

This patch mainly contains:
1. built-in function __gen_ocl_ime implementation.
2. Lots of built-in functions of cl_intel_device_side_avc_motion_estimation
   are implemented.
3. This extension is required to run in simd16 mode.

v2: move the utests to seprate patches one by one;
    as all the utests has extension function check, no need to put them
    in stand alone utest;
    uncomment the self test;
    fix extension check logic issue, should be && instead of ||.

Signed-off-by: Chuanbo Weng <chuanbo.weng@intel.com>
Signed-off-by: Xionghu Luo <xionghu.luo@intel.com>
Reviewed-by: Yang Rong <rong.r.yang@intel.com>

1 files changed, 63 insertions, 0 deletions

diff --git a/src/intel/intel_structs.h b/src/intel/intel_structs.h
index b38cc423..282929d7 100644
--- a/src/intel/intel_structs.h
+++ b/src/intel/intel_structs.h
@@ -425,6 +425,69 @@ typedef struct gen7_media_surface_state
   } ss7;
 } gen7_media_surface_state_t;
 
+typedef struct gen9_media_surface_state
+{
+  struct {
+    uint32_t pad3:12;
+    uint32_t pad2:4;
+    uint32_t pad1:11; //ExistsIf [Surface Format] is not one of Planar Formats
+    uint32_t rotation:2;
+  } ss0;
+
+  struct {
+    uint32_t uv_offset_v_direction:2;
+    uint32_t pic_struct:2;
+    uint32_t width:14;
+    uint32_t height:14;
+  } ss1;
+
+  struct {
+    uint32_t tile_mode:2;
+    uint32_t half_pitch_for_chroma:1;
+    uint32_t surface_pitch:18;
+    uint32_t address_control:1;
+    uint32_t mem_compress_enable:1;
+    uint32_t mem_compress_mode:1;
+    uint32_t uv_offset_v_direction_msb:1;
+    uint32_t uv_offset_u_direction:1;
+    uint32_t interleave_chroma:1;
+    uint32_t surface_format:5;
+  } ss2;
+
+  struct {
+    uint32_t y_offset_for_u:14;
+    uint32_t pad1:2;
+    uint32_t x_offset_for_u:14;
+    uint32_t pad0:2;
+  } ss3;
+
+  struct {
+    uint32_t y_offset_for_v:15;
+    uint32_t pad1:1;
+    uint32_t x_offset_for_v:14;
+    uint32_t pad0:2;
+  } ss4;
+
+  struct {
+    uint32_t surface_object_control_state:7;
+    uint32_t pad2:11;
+    uint32_t tiled_res_mode:2;
+    uint32_t pad1:4;
+    uint32_t pad0:6;
+    uint32_t vert_line_stride_offset:1;
+    uint32_t vert_line_stride:1;
+  } ss5;
+
+  struct {
+    uint32_t base_addr;
+  } ss6;
+
+  struct {
+    uint32_t base_addr_high:16;
+    uint32_t pad0:16;
+  } ss7;
+} gen9_media_surface_state_t;
+
 typedef union gen_surface_state
 {
   gen7_surface_state_t gen7_surface_state;