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| author | Song, Ruiling <ruiling.song@intel.com> | 2017-07-21 14:46:41 +0800 |
|---|---|---|
| committer | Yang Rong <rong.r.yang@intel.com> | 2017-07-27 16:19:32 +0800 |
| commit | 705e73c7873e11a14fcc308fafd1c26bc188021f (patch) | |
| tree | 19526f7cfb0d5d4370a634d5847485348c2560e9 /kernels/compiler_ceil32.spir | |
| parent | 9b7ca443cf7bee8105e819ef2893ee412a75fd30 (diff) | |
backend: Fix a bug in load-store optimization.
when we are merging STOREs, we should use the very last instruction
as the insertion point.
Signed-off-by: Ruiling Song <ruiling.song@intel.com>
Reviewed-by: Yang Rong <rong.r.yang@intel.com>
Diffstat (limited to 'kernels/compiler_ceil32.spir')
0 files changed, 0 insertions, 0 deletions