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| author | rander <rander.wang@intel.com> | 2017-07-04 15:20:08 +0800 |
|---|---|---|
| committer | Yang Rong <rong.r.yang@intel.com> | 2017-07-06 17:51:59 +0800 |
| commit | 49b63a260c66fc9438ad8b29344d8e1a4ba0285f (patch) | |
| tree | 4be699915f8d298500aeb8b2aeb240eed0d069ec /benchmark | |
| parent | 3ece4846013dc213686a372ddf630e34e435ea5c (diff) | |
backend: refine fdiv to rcp at some cases
when the src0 of fdiv is a immedia value and it is
exactly pow of 2, like 2.0f, 4.0f, 1.0/8.0f,
fdiv %0, imm, %1 can be convert to
rcp %0, %1
mul %0, %0, imm.
for fdiv cost 8cycle, rcp 4cycle. it will save at least
3cycle.
pass the conformance test and utests
V2: refine negation flag
V3: modify negation by negate
Signed-off-by: rander.wang <rander.wang@intel.com>
Reviewed-by: Yang Rong <rong.r.yang@intel.com>
Diffstat (limited to 'benchmark')
0 files changed, 0 insertions, 0 deletions