diff options
| author | Yang Rong <rong.r.yang@intel.com> | 2014-05-19 13:52:18 +0800 |
|---|---|---|
| committer | Zhigang Gong <zhigang.gong@intel.com> | 2014-05-19 12:46:15 +0800 |
| commit | 2cfa1d3e30f276b0f50f97b2fa661f31289acd2b (patch) | |
| tree | 70945fc8b3f9c1ae38f3633a4dda4b1fcc68e8f1 | |
| parent | 31ff786aca19847cde402d55e9d7ef20b15c9d52 (diff) | |
HSW: align buffer's size to DWORD.
HSW: Byte scattered Read/Write require that the buffer size must be a multiple of 4 bytes.
So simply alignment all buffer size to 4. Pass utest compiler_function_constant0.
Because it is very light work around, align it without not check device.
Signed-off-by: Yang Rong <rong.r.yang@intel.com>
Reviewed-by: Junyan He <junyan.he@inbox.com>
| -rw-r--r-- | src/cl_mem.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/cl_mem.c b/src/cl_mem.c index 5faef4bc..6b8ca7cd 100644 --- a/src/cl_mem.c +++ b/src/cl_mem.c @@ -334,6 +334,10 @@ cl_mem_new_buffer(cl_context ctx, goto error; } + /* HSW: Byte scattered Read/Write has limitation that + the buffer size must be a multiple of 4 bytes. */ + sz = ALIGN(sz, 4); + /* Create the buffer in video memory */ mem = cl_mem_allocate(CL_MEM_BUFFER_TYPE, ctx, flags, sz, CL_FALSE, &err); if (mem == NULL || err != CL_SUCCESS) |