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2014-10-21xtensa: nommu: don't build most of the cache flushing codeMax Filippov1-2/+2
Most cache flushing code is only relevant for MMU. Don't build it for nommu configuration. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-04-06xtensa: add HIGHMEM supportMax Filippov1-0/+1
Introduce fixmap area just below the vmalloc region. Use it for atomic mapping of high memory pages. High memory on cores with cache aliasing is not supported and is still to be implemented. Fail build for such configurations for now. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2009-04-02xtensa: nommu supportJohannes Weiner1-1/+2
Add support for !CONFIG_MMU setups. Signed-off-by: Johannes Weiner <jw@emlix.com> Signed-off-by: Chris Zankel <chris@zankel.net>
2008-01-28Remove references to "make dep"Adrian Bunk1-4/+0
"make dep" is no longer required in kernel 2.6, but was still mentioned in some places. Signed-off-by: Adrian Bunk <bunk@kernel.org> Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
2007-08-27[XTENSA] Add support for cache-aliasingChris Zankel1-5/+1
Add support for processors that have cache-aliasing issues, such as the Stretch S5000 processor. Cache-aliasing means that the size of the cache (for one way) is larger than the page size, thus, a page can end up in several places in cache depending on the virtual to physical translation. The method used here is to map a user page temporarily through the auto-refill way 0 and of of the DTLB. We probably will want to revisit this issue and use a better approach with kmap/kunmap. Signed-off-by: Chris Zankel <chris@zankel.net>
2005-06-24[PATCH] xtensa: Architecture support for Tensilica Xtensa Part 5Chris Zankel1-0/+13
The attached patches provides part 5 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>