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authorXiubo Li <Li.Xiubo@freescale.com>2014-02-11 15:42:48 +0800
committerMark Brown <broonie@linaro.org>2014-02-12 15:31:45 +0000
commit86f28d76435b619bd0bc5f6fde2803a5bc27ca24 (patch)
treeaf128fa11e486bc5c4124435ae9735745851e2b7 /virt
parent38dbfb59d1175ef458d006556061adeaa8751b72 (diff)
ASoC: fsl-spdif: big-endian support
For most platforms, the CPU and SPDIF device is in the same endianess mode. While for the LS1 platform, the CPU is in LE mode and the SPDIF is in BE mode. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Acked-by: Nicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
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