diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2015-03-12 17:10:38 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-03-20 11:48:09 +0100 |
| commit | fe51bfb95c996733150c44d21e1c9f4b6322a326 (patch) | |
| tree | 3d78fa7990112cb3678e01bcd2084b8945135b70 /drivers/gpu | |
| parent | e6bda3e4cb439679946c9378628d906ab32bf590 (diff) | |
drm/i915: Add eDP intermediate frequencies for CHV
"P1273_DPLL_Programming Spreadsheet.xlsm" lists a boatload of
frequencies for eDP. Try to use them all.
For now I've decided not to add hardcoded DPLL dividers for these cases
since chv_find_best_dpll() works just fine.
I've not actually tested any of these since I don't have an eDP 1.4 panel.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Sonika Jindal <sonika.jindal@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index ff0aa6f87679..ce0bdec4b6f9 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -87,6 +87,9 @@ static const struct dp_link_dpll chv_dpll[] = { /* Skylake supports following rates */ static const int gen9_rates[] = { 162000, 216000, 270000, 324000, 432000, 540000 }; +static const int chv_rates[] = { 162000, 202500, 210000, 216000, + 243000, 270000, 324000, 405000, + 420000, 432000, 540000 }; static const int default_rates[] = { 162000, 270000, 540000 }; /** @@ -1148,6 +1151,9 @@ intel_dp_source_rates(struct drm_device *dev, const int **source_rates) if (INTEL_INFO(dev)->gen >= 9) { *source_rates = gen9_rates; return ARRAY_SIZE(gen9_rates); + } else if (IS_CHERRYVIEW(dev)) { + *source_rates = chv_rates; + return ARRAY_SIZE(chv_rates); } *source_rates = default_rates; |