diff options
| author | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-08-20 16:30:32 +0800 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-08-20 16:30:32 +0800 |
| commit | 817faa6b00b042d6021d2cfb02ff7a18c98526ce (patch) | |
| tree | b106ff47f05fdac748993564c515871b413e089d | |
| parent | f5c9a7cba6859686c4e9aec530745ac851d6a568 (diff) | |
i965: fix cc state pointers orderHEADsandybridge
Also fix depth buffer width setting. But depth test still looks
wrong.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_misc_state.c | 11 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen6_cc.c | 4 |
2 files changed, 8 insertions, 7 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 572175f463e..5a5952b2e8f 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -281,7 +281,7 @@ static void emit_depthbuffer(struct brw_context *brw) } assert(region->tiling != I915_TILING_X); - if (IS_GEN6(intel->intelScreen->deviceID)) + if (intel->gen == 6) assert(region->tiling != I915_TILING_NONE); BEGIN_BATCH(len); @@ -289,13 +289,13 @@ static void emit_depthbuffer(struct brw_context *brw) OUT_BATCH(((region->pitch * region->cpp) - 1) | (format << 18) | (BRW_TILEWALK_YMAJOR << 26) | - ((region->tiling != I915_TILING_NONE) << 27) | + (1 << 27) | (BRW_SURFACE_2D << 29)); OUT_RELOC(region->buffer, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) | - ((region->pitch - 1) << 6) | + ((region->width - 1) << 6) | ((region->height - 1) << 19)); OUT_BATCH(0); @@ -309,9 +309,10 @@ static void emit_depthbuffer(struct brw_context *brw) } /* Initialize it for safety. */ - if (intel->gen >= 6) { + if (intel->gen >= 5) { BEGIN_BATCH(2); - OUT_BATCH(CMD_3D_CLEAR_PARAMS << 16 | (2 - 2)); + OUT_BATCH(CMD_3D_CLEAR_PARAMS << 16 | (2 - 2) | + DEPTH_CLEAR_VALID); OUT_BATCH(0); ADVANCE_BATCH(); } diff --git a/src/mesa/drivers/dri/i965/gen6_cc.c b/src/mesa/drivers/dri/i965/gen6_cc.c index f7acad69129..73ee24564c1 100644 --- a/src/mesa/drivers/dri/i965/gen6_cc.c +++ b/src/mesa/drivers/dri/i965/gen6_cc.c @@ -267,9 +267,9 @@ static void upload_cc_state_pointers(struct brw_context *brw) BEGIN_BATCH(4); OUT_BATCH(CMD_3D_CC_STATE_POINTERS << 16 | (4 - 2)); - OUT_RELOC(brw->cc.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1); OUT_RELOC(brw->cc.blend_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1); OUT_RELOC(brw->cc.depth_stencil_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1); + OUT_RELOC(brw->cc.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1); ADVANCE_BATCH(); intel_batchbuffer_emit_mi_flush(intel->batch); @@ -278,9 +278,9 @@ static void upload_cc_state_pointers(struct brw_context *brw) static void prepare_cc_state_pointers(struct brw_context *brw) { - brw_add_validated_bo(brw, brw->cc.state_bo); brw_add_validated_bo(brw, brw->cc.blend_state_bo); brw_add_validated_bo(brw, brw->cc.depth_stencil_state_bo); + brw_add_validated_bo(brw, brw->cc.state_bo); } const struct brw_tracked_state gen6_cc_state_pointers = { |