diff options
| author | Zhao Yakui <yakui.zhao@intel.com> | 2012-05-28 05:58:09 -0400 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2012-06-05 15:39:22 +0800 |
| commit | 5f26f5dbb6219199cd2382e3b6d74c7dce1c721f (patch) | |
| tree | eb1dd899eb4df9e989e6fe29ba7d543022cb2024 | |
| parent | 3f3b4608409b270fe6e94020f3b97116ae6a6289 (diff) | |
Disable the clock gating of display controller to make DP/eDP work wellcdv-3.2
I don't know why the DP/eDP is affected by the clock gating. But the test
shows that it really fixes the DP/eDP clock issue during enabling DP/eDP.
Fix the issue in https://lecutus.jf.intel.com/ceg/ticket/300
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
| -rw-r--r-- | drivers/staging/cdv/drv/psb_fb.c | 19 | ||||
| -rw-r--r-- | drivers/staging/cdv/drv/psb_intel_drv.h | 2 | ||||
| -rw-r--r-- | drivers/staging/cdv/drv/psb_intel_reg.h | 4 | ||||
| -rw-r--r-- | drivers/staging/cdv/drv/psb_powermgmt.c | 2 |
4 files changed, 27 insertions, 0 deletions
diff --git a/drivers/staging/cdv/drv/psb_fb.c b/drivers/staging/cdv/drv/psb_fb.c index 65dee822530..6e6d3488179 100644 --- a/drivers/staging/cdv/drv/psb_fb.c +++ b/drivers/staging/cdv/drv/psb_fb.c @@ -735,6 +735,23 @@ static int psb_bo_unpin_for_scanout(struct drm_device *dev, void *bo) return 0; } +/* Cedarview display clock gating */ +void psb_intel_clock_gating (struct drm_device *dev) +{ + uint32_t reg_value; + reg_value = REG_READ(DSPCLK_GATE_D); + + reg_value |= (DPUNIT_PIPEB_GATE_DISABLE | + DPUNIT_PIPEA_GATE_DISABLE | + DPCUNIT_CLOCK_GATE_DISABLE | + DPLSUNIT_CLOCK_GATE_DISABLE | + DPOUNIT_CLOCK_GATE_DISABLE | + DPIOUNIT_CLOCK_GATE_DISABLE); + + REG_WRITE(DSPCLK_GATE_D, reg_value); + + udelay(500); +} /* Cedarview display workarounds */ void psb_intel_display_wa (struct drm_device *dev) { @@ -771,6 +788,8 @@ void psb_modeset_init(struct drm_device *dev) drm_mode_config_init(dev); + psb_intel_clock_gating(dev); + dev->mode_config.min_width = 0; dev->mode_config.min_height = 0; diff --git a/drivers/staging/cdv/drv/psb_intel_drv.h b/drivers/staging/cdv/drv/psb_intel_drv.h index 2f4d40dd519..7b1443d73f9 100644 --- a/drivers/staging/cdv/drv/psb_intel_drv.h +++ b/drivers/staging/cdv/drv/psb_intel_drv.h @@ -281,4 +281,6 @@ extern u32 psb_intel_panel_get_backlight(struct drm_device *dev); extern void psb_intel_panel_destroy_backlight(struct drm_device *dev); extern int psb_intel_panel_setup_backlight(struct drm_device *dev); + +extern void psb_intel_clock_gating (struct drm_device *dev); #endif /* __INTEL_DRV_H__ */ diff --git a/drivers/staging/cdv/drv/psb_intel_reg.h b/drivers/staging/cdv/drv/psb_intel_reg.h index 20265dac641..f0bfb0c4c29 100644 --- a/drivers/staging/cdv/drv/psb_intel_reg.h +++ b/drivers/staging/cdv/drv/psb_intel_reg.h @@ -1402,6 +1402,10 @@ gamma settings. # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* Fixed value on CDV */ # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) +# define DPUNIT_PIPEB_GATE_DISABLE (1 << 30) +# define DPUNIT_PIPEA_GATE_DISABLE (1 << 25) +# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) +# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) #define RAMCLK_GATE_D 0x6210 diff --git a/drivers/staging/cdv/drv/psb_powermgmt.c b/drivers/staging/cdv/drv/psb_powermgmt.c index 8bb69990282..33ead94c3b8 100644 --- a/drivers/staging/cdv/drv/psb_powermgmt.c +++ b/drivers/staging/cdv/drv/psb_powermgmt.c @@ -563,6 +563,8 @@ int ospm_power_resume(struct pci_dev *pdev) ospm_resume_pci(pdev); + psb_intel_clock_gating(gpDrmDevice); + psb_intel_opregion_setup(gpDrmDevice); /* resume PVR power island and service */ |