diff options
| author | Luo Xionghu <xionghu.luo@intel.com> | 2014-09-15 08:23:37 +0800 |
|---|---|---|
| committer | Zhigang Gong <zhigang.gong@intel.com> | 2014-09-26 12:56:37 +0800 |
| commit | 13d8e51dca732758592f8f4826f0bc4d21ec5553 (patch) | |
| tree | 19968b0d077020fc89009e1f2fcb6f61fda14d95 | |
| parent | c0ba37d62dcac92adfc309e73abd7e12a02d8498 (diff) | |
Add Gen IR WHILE.
Add Gen IR WHILE to mark the strucutred region.
Signed-off-by: Luo Xionghu <xionghu.luo@intel.com>
Reviewed-by: Zhigang Gong <zhigang.gong@linux.intel.com>
| -rw-r--r-- | backend/src/ir/instruction.cpp | 7 | ||||
| -rw-r--r-- | backend/src/ir/instruction.hpp | 2 | ||||
| -rw-r--r-- | backend/src/ir/instruction.hxx | 1 |
3 files changed, 9 insertions, 1 deletions
diff --git a/backend/src/ir/instruction.cpp b/backend/src/ir/instruction.cpp index 2d86480..e4e30ed 100644 --- a/backend/src/ir/instruction.cpp +++ b/backend/src/ir/instruction.cpp @@ -349,7 +349,7 @@ namespace ir { { public: INLINE BranchInstruction(Opcode op, LabelIndex labelIndex, Register predicate, bool inv_pred=false) { - GBE_ASSERT(op == OP_BRA || op == OP_IF); + GBE_ASSERT(op == OP_BRA || op == OP_IF || op == OP_WHILE); this->opcode = op; this->predicate = predicate; this->labelIndex = labelIndex; @@ -1721,6 +1721,11 @@ DECL_MEM_FN(GetImageInfoInstruction, uint8_t, getImageIndex(void), getImageIndex return internal::BranchInstruction(OP_ENDIF, labelIndex).convert(); } + // WHILE + Instruction WHILE(LabelIndex labelIndex, Register pred) { + return internal::BranchInstruction(OP_WHILE, labelIndex, pred).convert(); + } + // RET Instruction RET(void) { return internal::BranchInstruction(OP_RET).convert(); diff --git a/backend/src/ir/instruction.hpp b/backend/src/ir/instruction.hpp index 3526a41..6807615 100644 --- a/backend/src/ir/instruction.hpp +++ b/backend/src/ir/instruction.hpp @@ -687,6 +687,8 @@ namespace ir { Instruction ELSE(LabelIndex labelIndex); /*! endif */ Instruction ENDIF(LabelIndex labelIndex); + /*! (pred) while labelIndex */ + Instruction WHILE(LabelIndex labelIndex, Register pred); /*! ret */ Instruction RET(void); /*! load.type.space {dst1,...,dst_valueNum} offset value */ diff --git a/backend/src/ir/instruction.hxx b/backend/src/ir/instruction.hxx index 40b5305..5fed286 100644 --- a/backend/src/ir/instruction.hxx +++ b/backend/src/ir/instruction.hxx @@ -98,3 +98,4 @@ DECL_INSN(MAD, TernaryInstruction) DECL_INSN(IF, BranchInstruction) DECL_INSN(ENDIF, BranchInstruction) DECL_INSN(ELSE, BranchInstruction) +DECL_INSN(WHILE, BranchInstruction) |