R600/SI: Start working on a Scheduler for SI.radeonsi-backup

5 files changed, 71 insertions, 14 deletions

diff --git a/lib/Target/R600/AMDGPU.td b/lib/Target/R600/AMDGPU.td
index d1e2cf5319..a459044c99 100644
--- a/lib/Target/R600/AMDGPU.td
+++ b/lib/Target/R600/AMDGPU.td
@@ -122,10 +122,10 @@ def AMDGPU : Target {
 
 // Include AMDGPU TD files
 include "R600Schedule.td"
-include "SISchedule.td"
-include "Processors.td"
 include "AMDGPUInstrInfo.td"
 include "AMDGPUIntrinsics.td"
 include "AMDGPURegisterInfo.td"
 include "AMDGPUInstructions.td"
 include "AMDGPUCallingConv.td"
+include "SISchedule.td"
+include "Processors.td"
diff --git a/lib/Target/R600/AMDGPUSubtarget.cpp b/lib/Target/R600/AMDGPUSubtarget.cpp
index e77ab5e6d1..28074f9cac 100644
--- a/lib/Target/R600/AMDGPUSubtarget.cpp
+++ b/lib/Target/R600/AMDGPUSubtarget.cpp
@@ -13,6 +13,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "AMDGPUSubtarget.h"
+#include "llvm/CodeGen/MachineScheduler.h"
 
 using namespace llvm;
 
@@ -119,3 +120,11 @@ std::string
 AMDGPUSubtarget::getDeviceName() const {
   return DevName;
 }
+
+void
+AMDGPUSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
+                                     MachineInstr *begin, MachineInstr *end,
+                                     unsigned NumRegionInstrs) const {
+  Policy.OnlyTopDown = true;
+//  Policy.OnlyBottomUp = false;
+}
diff --git a/lib/Target/R600/AMDGPUSubtarget.h b/lib/Target/R600/AMDGPUSubtarget.h
index 7cf102cff6..3bf34c8b24 100644
--- a/lib/Target/R600/AMDGPUSubtarget.h
+++ b/lib/Target/R600/AMDGPUSubtarget.h
@@ -93,9 +93,12 @@ public:
   bool hasCFAluBug() const;
 
   virtual bool enableMachineScheduler() const {
-    return getGeneration() <= NORTHERN_ISLANDS;
+    return true;
   }
 
+  void overrideSchedPolicy(MachineSchedPolicy &Policy, MachineInstr *begin,
+                           MachineInstr *end, unsigned NumRegionInstrs) const;
+
   // Helper functions to simplify if statements
   bool isTargetELF() const;
   std::string getDeviceName() const;
diff --git a/lib/Target/R600/Processors.td b/lib/Target/R600/Processors.td
index fde4481497..0ee94d93e0 100644
--- a/lib/Target/R600/Processors.td
+++ b/lib/Target/R600/Processors.td
@@ -83,26 +83,26 @@ def : Proc<"cayman",     R600_VLIW4_Itin,
 // Southern Islands
 //===----------------------------------------------------------------------===//
 
-def : Proc<"SI",         SI_Itin, [FeatureSouthernIslands]>;
+def : ProcessorModel<"SI",         SIModel, [FeatureSouthernIslands]>;
 
-def : Proc<"tahiti",     SI_Itin, [FeatureSouthernIslands]>;
+def : ProcessorModel<"tahiti",     SIModel, [FeatureSouthernIslands]>;
 
-def : Proc<"pitcairn",   SI_Itin, [FeatureSouthernIslands]>;
+def : ProcessorModel<"pitcairn",   SIModel, [FeatureSouthernIslands]>;
 
-def : Proc<"verde",      SI_Itin, [FeatureSouthernIslands]>;
+def : ProcessorModel<"verde",      SIModel, [FeatureSouthernIslands]>;
 
-def : Proc<"oland",      SI_Itin, [FeatureSouthernIslands]>;
+def : ProcessorModel<"oland",      SIModel, [FeatureSouthernIslands]>;
 
-def : Proc<"hainan",     SI_Itin, [FeatureSouthernIslands]>;
+def : ProcessorModel<"hainan",     SIModel, [FeatureSouthernIslands]>;
 
 //===----------------------------------------------------------------------===//
 // Sea Islands
 //===----------------------------------------------------------------------===//
 
-def : Proc<"bonaire",    SI_Itin, [FeatureSeaIslands]>;
+def : ProcessorModel<"bonaire",    SIModel, [FeatureSeaIslands]>;
 
-def : Proc<"kabini",     SI_Itin, [FeatureSeaIslands]>;
+def : ProcessorModel<"kabini",     SIModel, [FeatureSeaIslands]>;
 
-def : Proc<"kaveri",     SI_Itin, [FeatureSeaIslands]>;
+def : ProcessorModel<"kaveri",     SIModel, [FeatureSeaIslands]>;
 
-def : Proc<"hawaii",     SI_Itin, [FeatureSeaIslands]>;
+def : ProcessorModel<"hawaii",     SIModel, [FeatureSeaIslands]>;
diff --git a/lib/Target/R600/SISchedule.td b/lib/Target/R600/SISchedule.td
index 28b65b8258..bd47aab402 100644
--- a/lib/Target/R600/SISchedule.td
+++ b/lib/Target/R600/SISchedule.td
@@ -11,5 +11,50 @@
 //
 //===----------------------------------------------------------------------===//
 
+def SIModel : SchedMachineModel {
+  let IssueWidth = 2;
+  let MicroOpBufferSize = 0; // SI is in order
+  let LoadLatency = 4; // Depends a lot of the memory read
+  let CompleteModel = 0;
+}
+
+// We consider SI having 3 execution units at the moment :
+// - One for vector ALU
+// - One for scalar ALU
+// - One for memory access
+// Actually scalar instructions are run by the same unit as vector ones but
+// can hide their execution when running concurrently a scalar and a vector
+// instruction accross wavefronts
+
+def VectorUnit : ProcResource<1> {
+  let BufferSize = 0;
+}
+
+def ScalarUnit : ProcResource<1> {
+  let BufferSize = 0;
+}
+
+def LoadStoreUnit : ProcResource<1> {
+  let BufferSize = 0;
+}
+
+def WriteVector : SchedWrite;
+def WriteScalar : SchedWrite;
+
+let SchedModel = SIModel in {
+def : WriteRes<WriteVector, [VectorUnit]>
+{
+  let Latency = 1;
+  let ResourceCycles = [1];
+}
+def : WriteRes<WriteScalar, [ScalarUnit]>
+{
+  let Latency = 2;
+  let ResourceCycles = [2];
+}
+
+def : InstRW<[WriteScalar], (instrs S_BUFFER_LOAD_DWORD_IMM)>;
+def : InstRW<[WriteVector], (instrs V_MUL_F32_e32, V_MAD_F32, V_ADD_F32_e64)>;
+}
+
 
-def SI_Itin : ProcessorItineraries <[], [], []>;