| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2012-12-27 | On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized | Nadav Rotem | 1 | -0/+38 |
| 2012-12-26 | llvm/test/CodeGen/X86: FileCheck-ize two tests in r171083. | NAKAMURA Takumi | 2 | -2/+17 |
| 2012-12-26 | llvm/test/CodeGen/X86: Disable avx in two tests corresponding to r171082. | NAKAMURA Takumi | 2 | -2/+2 |
| 2012-12-25 | Loosen scheduling restrictions on the PPC dcbt intrinsic | Hal Finkel | 1 | -0/+22 |
| 2012-12-25 | Expand PPC64 atomic load and store | Hal Finkel | 1 | -0/+20 |
| 2012-12-25 | Harden test so it's not affected by changes to compare lowering. | Benjamin Kramer | 1 | -1/+1 |
| 2012-12-25 | X86: Shave off one shuffle from the pcmpeqq sequence for SSE2 by making use o... | Benjamin Kramer | 1 | -4/+2 |
| 2012-12-25 | X86: Custom lower <2 x i64> eq and ne when SSE41 is not available. | Benjamin Kramer | 1 | -0/+26 |
| 2012-12-24 | llvm/test/CodeGen/X86/fold-vex.ll: Add explicit triple. | NAKAMURA Takumi | 1 | -1/+1 |
| 2012-12-24 | Some x86 instructions can load/store one of the operands to memory. On SSE, t... | Nadav Rotem | 1 | -0/+16 |
| 2012-12-22 | X86: Turn mul of <4 x i32> into pmuludq when no SSE4.1 is available. | Benjamin Kramer | 1 | -0/+14 |
| 2012-12-22 | X86: Emit vector sext as shuffle + sra if vpmovsx is not available. | Benjamin Kramer | 1 | -23/+96 |
| 2012-12-21 | In some cases, due to scheduling constraints we copy the EFLAGS. | Nadav Rotem | 1 | -0/+37 |
| 2012-12-21 | try to unbreak ppc buildbots. | Benjamin Kramer | 1 | -4/+4 |
| 2012-12-21 | X86: Match pmin/pmax as a target specific dag combine. This occurs during vec... | Benjamin Kramer | 2 | -3/+2790 |
| 2012-12-21 | R600: Expand vec4 INT <-> FP conversions | Tom Stellard | 1 | -0/+52 |
| 2012-12-21 | Add test case for r170674 | Reed Kotler | 1 | -0/+29 |
| 2012-12-21 | Move these files over to the debug info directory. | Eric Christopher | 2 | -112/+0 |
| 2012-12-20 | Revert "Adding support for llvm.arm.neon.vaddl[su].* and" | Bob Wilson | 2 | -128/+0 |
| 2012-12-20 | On some ARM cpus, flags setting movs with shifter operand, i.e. lsl, lsr, asr, | Evan Cheng | 1 | -13/+69 |
| 2012-12-20 | Simplify the testcase a bit. | Rafael Espindola | 1 | -15/+4 |
| 2012-12-20 | Adding support for llvm.arm.neon.vaddl[su].* and | Renato Golin | 2 | -0/+128 |
| 2012-12-20 | fix most of remaining issues with large frames. | Reed Kotler | 1 | -2/+2 |
| 2012-12-20 | [mips] Use "or $r0, $r1, $zero" instead of "addu $r0, $zero, $r1" to copy | Akira Hatanaka | 6 | -18/+18 |
| 2012-12-20 | Do not introduce vector operations in functions marked with noimplicitfloat. | Bob Wilson | 1 | -0/+17 |
| 2012-12-19 | LLVM sdisel normalize bit extraction of the form: | Evan Cheng | 1 | -0/+25 |
| 2012-12-19 | PowerPC: Expand VSELECT nodes. | Benjamin Kramer | 1 | -0/+7 |
| 2012-12-19 | Optimized load + SIGN_EXTEND patterns in the X86 backend. | Elena Demikhovsky | 3 | -3/+98 |
| 2012-12-19 | After reducing the size of an operation in the DAG we zero-extend the reduced | Nadav Rotem | 1 | -0/+21 |
| 2012-12-19 | Teach SimplifySetCC that comparing AssertZext i1 against a constant 1 can be ... | Craig Topper | 1 | -0/+15 |
| 2012-12-18 | Disable ARM partial flag dependency optimization at -Oz | Quentin Colombet | 1 | -0/+34 |
| 2012-12-18 | MISched: add dependence to ExitSU to model live-out latency. | Andrew Trick | 1 | -0/+48 |
| 2012-12-18 | Check multiple register classes for inline asm tied registers | Hal Finkel | 1 | -0/+22 |
| 2012-12-17 | Add rest of BMI/BMI2 instructions to the folding tables as well as popcnt and... | Craig Topper | 1 | -0/+76 |
| 2012-12-16 | This patch is needed to make c++ exceptions work for mips16. | Reed Kotler | 1 | -0/+87 |
| 2012-12-15 | X86: Add a couple of target-specific dag combines that turn VSELECTS into psu... | Benjamin Kramer | 1 | -0/+340 |
| 2012-12-15 | This code implements most of mips16 hardfloat as it is done by gcc. | Reed Kotler | 1 | -0/+381 |
| 2012-12-14 | TypeLegalizer: Do not generate target specific nodes with illegal types, beca... | Nadav Rotem | 1 | -0/+22 |
| 2012-12-14 | This patch removes some nondeterminism from direct object file output | Bill Schmidt | 1 | -4/+0 |
| 2012-12-14 | This patch improves the 64-bit PowerPC InitialExec TLS support by providing | Bill Schmidt | 2 | -3/+8 |
| 2012-12-13 | [mips] Do not copy GOT address to register $gp if the function being called has | Akira Hatanaka | 1 | -0/+27 |
| 2012-12-13 | Fix a bug in DAGCombiner::MatchBSwapHWord. Make sure the node has operands be... | Evan Cheng | 1 | -0/+46 |
| 2012-12-12 | Fix a logic bug in inline expansion of memcpy / memset with an overlapping | Evan Cheng | 1 | -0/+11 |
| 2012-12-12 | The ordering of two relocations on the same instruction is apparently not | Bill Schmidt | 1 | -3/+8 |
| 2012-12-12 | This patch implements local-dynamic TLS model support for the 64-bit | Bill Schmidt | 2 | -0/+73 |
| 2012-12-12 | llvm/test/CodeGen/X86/atom-bypass-slow-division.ll: Fix possible typo(s) in C... | NAKAMURA Takumi | 1 | -4/+4 |
| 2012-12-12 | llvm/test/CodeGen/X86/atom-bypass-slow-division.ll: Rename symbols, s/test_/T... | NAKAMURA Takumi | 1 | -20/+20 |
| 2012-12-12 | llvm/test/CodeGen/X86/store_op_load_fold.ll: Fix typo, s/CHECK_NEXT/CHECK-NEXT/ | NAKAMURA Takumi | 1 | -1/+1 |
| 2012-12-12 | llvm/test/CodeGen/X86/store_op_load_fold.ll: Add explicit triple. | NAKAMURA Takumi | 1 | -1/+1 |
| 2012-12-12 | DAGCombine: clamp hi bit in APInt::getBitsSet to avoid assertion | Manman Ren | 1 | -1/+18 |
