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2012-12-27Make this parameter be named consistently with most otherChandler Carruth1-2/+2
2012-12-27[ASan] Fix lifetime intrinsics handling. Now for each intrinsic we check if i...Alexey Samsonov1-69/+91
2012-12-27On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sizedNadav Rotem1-15/+106
2012-12-27AVX/AVX2: Move the code that lowers vector-trunc from a DAGCo-hook to custom ...Nadav Rotem1-106/+96
2012-12-27Add hasSideEffects=0 to some forms of ROUND, RCP, and RSQRT.Craig Topper1-0/+3
2012-12-27Refactor DAGCombinerInfo. Change the different booleans that indicate if we a...Nadav Rotem2-3/+3
2012-12-27Move single letter 'P' prefix out of multiclass now that tablegen allows defm...Craig Topper1-86/+85
2012-12-27Update tablegen parser to allow defm names to start with #NAME.Craig Topper1-1/+5
2012-12-27Add hasSideEffects=0 to some shift and rotate instructions. None of which are...Craig Topper1-1/+5
2012-12-27Mark the divide instructions as hasSideEffects=0.Craig Topper1-0/+2
2012-12-27For the dwarf5 split debug info code split out the string sectionEric Christopher2-21/+53
2012-12-27Add hasSideEffects=0 to CMP*rr_REV.Craig Topper1-0/+1
2012-12-27Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC instructions...Craig Topper1-19/+43
2012-12-27Right now all of the relocations are 32-bit dwarf, and the relocationEric Christopher1-4/+3
2012-12-26If all of the write objects are identified then we can vectorize the loop eve...Nadav Rotem1-1/+5
2012-12-26Fix operands and encoding form for ARPL instruction. Register form had and ...Craig Topper1-2/+2
2012-12-26Add hasSideEffects=0 to some atomic instructions.Craig Topper1-1/+1
2012-12-26Mark the AL/AX/EAX forms of the basic arithmetic operations has never having ...Craig Topper1-43/+44
2012-12-2680 columns. No functionality change.Nick Lewycky1-1/+1
2012-12-26Remove mid-optimizer warning. This situation should be handled differently,Nick Lewycky1-5/+2
2012-12-26Mark all the _REV instructions as not having side effects. They aren't really...Craig Topper4-9/+10
2012-12-26Remove a special conditional setting of neverHasSideEffects if the instructio...Craig Topper1-4/+3
2012-12-26LoopVectorizer: Optimize the vectorization of consecutive memory access when ...Nadav Rotem2-23/+71
2012-12-26[msan] Raise alignment of origin stores/loads when possible.Evgeniy Stepanov1-5/+11
2012-12-26[msan] Expand the file comment with track-origins info.Evgeniy Stepanov1-5/+27
2012-12-26Merge still more SSE/AVX instruction definitions.Craig Topper1-43/+15
2012-12-26Merge more SSE/AVX instruction definitions.Craig Topper1-129/+49
2012-12-26Fix 80 column violation.Craig Topper1-2/+2
2012-12-26Fix class name in comment.Craig Topper1-1/+1
2012-12-26Merge SSE/AVX PCMPEQ/PCMPGT instruction definitions.Craig Topper1-62/+12
2012-12-26Remove 'v' from mnemonic to fix asm matching failures.Craig Topper1-1/+1
2012-12-26Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction def...Craig Topper1-108/+42
2012-12-26Reformat the docs.Nadav Rotem1-20/+7
2012-12-26Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction def...Craig Topper1-30/+18
2012-12-26Merge an AVX/SSE 256-bit and 128-bit multiclass.Craig Topper1-26/+15
2012-12-26Mark VANDNPD/VANDNPDS as not commutable.Craig Topper1-1/+2
2012-12-26Remove alignment from a bunch more VEX encoded operations in the folding tables.Craig Topper1-47/+47
2012-12-26Remove alignment from folding table for VMOVUPD as an unaligned instruction i...Craig Topper1-1/+1
2012-12-26Remove alignment requirements from (V)EXTRACTPS. This instruction does 32-bit...Craig Topper1-2/+2
2012-12-26BBVectorize: Use VTTI to compute costs for intrinsics vectorizationHal Finkel1-12/+64
2012-12-26Remove alignment requirement from VCVTSS2SD in folding tables. Reverting r171...Craig Topper1-2/+2
2012-12-25LoopVectorize: Enable vectorization of the fmuladd intrinsicHal Finkel1-0/+1
2012-12-25BBVectorize: Enable vectorization of the fmuladd intrinsicHal Finkel1-0/+1
2012-12-25Expand PPC64 atomic load and storeHal Finkel1-0/+2
2012-12-25[msan] Fix handling of vectors of pointers.Evgeniy Stepanov1-2/+7
2012-12-25[msan] Fix handling of select with vector condition.Evgeniy Stepanov1-2/+11
2012-12-25X86: Shave off one shuffle from the pcmpeqq sequence for SSE2 by making use o...Benjamin Kramer1-6/+4
2012-12-25X86: Custom lower <2 x i64> eq and ne when SSE41 is not available.Benjamin Kramer1-2/+24
2012-12-25ASan: initialize callbacks from ASan module pass in a separate function for c...Alexey Samsonov1-21/+28
2012-12-25ASan: move stack poisoning logic into FunctionStackPoisoner structAlexey Samsonov1-190/+220
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