diff options
author | Tvrtko Ursulin <tvrtko.ursulin@intel.com> | 2018-03-14 17:10:21 +0000 |
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committer | Tvrtko Ursulin <tvrtko.ursulin@intel.com> | 2018-04-11 15:53:02 +0100 |
commit | cf0487895065ed794c46a1ff0debc24dae84d3bf (patch) | |
tree | b9d5e376f098645c03eac8ffd1eb4df7fc6bcabf | |
parent | 27cd3793a3a183e4ec70c392f293e840642f2799 (diff) |
tests/i915_query: Engine discovery testsengine-discovery
...
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
-rw-r--r-- | tests/i915_query.c | 310 |
1 files changed, 310 insertions, 0 deletions
diff --git a/tests/i915_query.c b/tests/i915_query.c index c7de8cbd..d3cdab32 100644 --- a/tests/i915_query.c +++ b/tests/i915_query.c @@ -477,6 +477,304 @@ test_query_topology_known_pci_ids(int fd, int devid) free(topo_info); } +#define DRM_I915_QUERY_ENGINE_INFO 2 + +/** + * struct drm_i915_engine_info + * + * Describes one engine known to the driver, whether or not is physical engine + * only, or it can also be targetted from userspace, and what are its + * capabilities where applicable. + */ +struct drm_i915_engine_info { + /** Engine flags. */ + __u64 flags; +#define I915_ENGINE_FLAG_PHYSICAL (1 << 0) +#define I915_ENGINE_FLAG_ABI (1 << 1) + + /** Engine class as in enum drm_i915_gem_engine_class. */ + __u16 class; + + /** Engine instance number. */ + __u16 instance; + + __u32 rsvd0; + + /** Capabilities of this engine. */ + __u64 capabilities; +#define I915_VCS_CLASS_CAPABILITY_HEVC (1 << 0) + + __u64 rsvd1[2]; +}; + +/** + * struct drm_i915_query_engine_info + * + * Engine info query enumerates all the engines known to the driver returning + * the array of struct drm_i915_engine_info structures. + */ +struct drm_i915_query_engine_info { + /** Number of struct drm_i915_engine_info structs following. */ + __u32 num_engines; + + /** MBZ */ + __u32 rsvd[3]; + + /** Marker for drm_i915_engine_info structures. */ + struct drm_i915_engine_info engines[]; +}; + +static bool query_engine_info_supported(int fd) +{ + struct drm_i915_query_item item = { + .query_id = DRM_I915_QUERY_ENGINE_INFO, + }; + + return __i915_query_items(fd, &item, 1) == 0 && item.length > 0; +} + +static void engines_invalid(int fd) +{ + struct drm_i915_query_engine_info *engines; + struct drm_i915_query_item item; + unsigned int len; + + /* Flags is MBZ. */ + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.flags = 1; + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EINVAL); + + /* Length not zero and not greater or equal required size. */ + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = 1; + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EINVAL); + + /* Query correct length. */ + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + i915_query_items(fd, &item, 1); + igt_assert(item.length >= 0); + len = item.length; + + engines = malloc(len); + igt_assert(engines); + + /* Ivalid pointer. */ + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EFAULT); + + /* All fields in engines query are MBZ and only filled by the kernel. */ + + memset(engines, 0, len); + engines->num_engines = 1; + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EINVAL); + + memset(engines, 0, len); + engines->rsvd[0] = 1; + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EINVAL); + + memset(engines, 0, len); + engines->rsvd[1] = 1; + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EINVAL); + + memset(engines, 0, len); + engines->rsvd[2] = 1; + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EINVAL); + + memset(engines, 0, len); + engines->engines[0].flags = 1; + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EINVAL); + + free(engines); + + igt_assert(len <= 4096); + engines = mmap(0, 4096, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON, + -1, 0); + igt_assert(engines != MAP_FAILED); + + /* PROT_NONE is similar to unmapped area. */ + memset(engines, 0, len); + igt_assert_eq(mprotect(engines, len, PROT_NONE), 0); + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EFAULT); + igt_assert_eq(mprotect(engines, len, PROT_WRITE), 0); + + /* Read-only so kernel cannot fill the data back. */ + memset(engines, 0, len); + igt_assert_eq(mprotect(engines, len, PROT_READ), 0); + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, -EFAULT); + + munmap(engines, 4096); +} + +static bool +has_engine(struct drm_i915_query_engine_info *engines, + unsigned class, unsigned instance) +{ + unsigned int i; + + for (i = 0; i < engines->num_engines; i++) { + struct drm_i915_engine_info *engine = + (struct drm_i915_engine_info *)&engines->engines[i]; + + if (engine->class == class && engine->instance == instance) + return true; + } + + return false; +} + +static void engines(int fd) +{ + struct drm_i915_query_engine_info *engines; + struct drm_i915_query_item item; + unsigned int len, i; + + engines = malloc(4096); + igt_assert(engines); + + /* Query required buffer length. */ + memset(engines, 0, 4096); + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert(item.length >= 0); + igt_assert(item.length <= 4096); + len = item.length; + + /* Check length larger than required works and reports same length. */ + memset(engines, 0, 4096); + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = 4096; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, len); + + /* Actual query. */ + memset(engines, 0, 4096); + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_ENGINE_INFO; + item.length = len; + item.data_ptr = to_user_pointer(engines); + i915_query_items(fd, &item, 1); + igt_assert_eq(item.length, len); + + /* Every GPU has at least one engine. */ + igt_assert(engines->num_engines > 0); + + /* MBZ fields. */ + igt_assert_eq(engines->rsvd[0], 0); + igt_assert_eq(engines->rsvd[1], 0); + igt_assert_eq(engines->rsvd[2], 0); + + /* Check results match the legacy GET_PARAM (where we can). */ + for (i = 0; i < engines->num_engines; i++) { + struct drm_i915_engine_info *engine = + (struct drm_i915_engine_info *)&engines->engines[i]; + + igt_debug("%u: class=%u instance=%u flags=%llx capabilities=%llx\n", + i, engine->class, engine->instance, engine->flags, + engine->capabilities); + + /* MBZ fields. */ + igt_assert_eq(engine->rsvd0, 0); + igt_assert_eq(engine->rsvd1[0], 0); + igt_assert_eq(engine->rsvd1[1], 0); + + /* Every engine has a type. */ + igt_assert(engine->flags); + + switch (engine->class) { + case I915_ENGINE_CLASS_RENDER: + /* Will be tested later. */ + break; + case I915_ENGINE_CLASS_COPY: + igt_assert(gem_has_blt(fd)); + break; + case I915_ENGINE_CLASS_VIDEO: + switch (engine->instance) { + case 0: + igt_assert(gem_has_bsd(fd)); + if (intel_gen(intel_get_drm_devid(fd)) >= 8) + igt_assert(engine->capabilities & + I915_VCS_CLASS_CAPABILITY_HEVC); + else + igt_assert(!(engine->capabilities & + I915_VCS_CLASS_CAPABILITY_HEVC)); + break; + case 1: + igt_assert(gem_has_bsd2(fd)); + igt_assert(!(engine->capabilities & + I915_VCS_CLASS_CAPABILITY_HEVC)); + break; + } + break; + case I915_ENGINE_CLASS_VIDEO_ENHANCE: + igt_assert(gem_has_vebox(fd)); + break; + default: + igt_assert(0); + } + } + + /* Reverse check to the above - all GET_PARAM engines are present. */ + igt_assert(has_engine(engines, I915_ENGINE_CLASS_RENDER, 0)); + if (gem_has_blt(fd)) + igt_assert(has_engine(engines, I915_ENGINE_CLASS_COPY, 0)); + if (gem_has_bsd(fd)) + igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO, 0)); + if (gem_has_bsd2(fd)) + igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO, 1)); + if (gem_has_vebox(fd)) + igt_assert(has_engine(engines, I915_ENGINE_CLASS_VIDEO_ENHANCE, + 0)); + + free(engines); +} + igt_main { int fd = -1; @@ -524,6 +822,18 @@ igt_main test_query_topology_known_pci_ids(fd, devid); } + igt_subtest_group { + igt_fixture { + igt_require(query_engine_info_supported(fd)); + } + + igt_subtest("engine-info-invalid") + engines_invalid(fd); + + igt_subtest("engine-info") + engines(fd); + } + igt_fixture { close(fd); } |