Reg rewrite wipllvm-reg-rewrite-wip

13 files changed, 221 insertions, 207 deletions

diff --git a/src/gallium/drivers/radeon/AMDGPUConstants.pm b/src/gallium/drivers/radeon/AMDGPUConstants.pm
index fde838daa83..722b664c9f6 100644
--- a/src/gallium/drivers/radeon/AMDGPUConstants.pm
+++ b/src/gallium/drivers/radeon/AMDGPUConstants.pm
@@ -27,9 +27,30 @@ package AMDGPUConstants;
 
 use base 'Exporter';
 
-use constant INPUT_REG_COUNT => 64;
-use constant CONST_REG_COUNT => 1024;
+use constant CONST_REG_COUNT => 256;
+use constant TEMP_REG_COUNT => 128;
 
-our @EXPORT = ('INPUT_REG_COUNT', 'CONST_REG_COUNT');
+our @EXPORT = ('TEMP_REG_COUNT', 'CONST_REG_COUNT', 'get_hw_index', 'get_chan_str');
+
+sub get_hw_index {
+  my ($index) = @_;
+  return int($index / 4);
+}
+
+sub get_chan_str {
+  my ($index) = @_;
+  my $chan = $index % 4;
+  if ($chan == 0 )  {
+    return 'X';
+  } elsif ($chan == 1) {
+    return 'Y';
+  } elsif ($chan == 2) {
+    return 'Z';
+  } elsif ($chan == 3) {
+    return 'W';
+  } else {
+    die("Unknown chan value: $chan");
+  }
+}
 
 1;
diff --git a/src/gallium/drivers/radeon/AMDGPUDelimitInstGroups.cpp b/src/gallium/drivers/radeon/AMDGPUDelimitInstGroups.cpp
index 7a45ecc1ad4..aa36f7bc30f 100644
--- a/src/gallium/drivers/radeon/AMDGPUDelimitInstGroups.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUDelimitInstGroups.cpp
@@ -27,9 +27,10 @@
 
 #include "AMDIL.h"
 #include "AMDGPU.h"
-#include "AMDGPURegisterInfo.h"
 #include "AMDGPUUtil.h"
 
+#include "R600RegisterInfo.h"
+
 #include "llvm/ADT/IndexedMap.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/Support/ErrorHandling.h"
@@ -79,8 +80,8 @@ FunctionPass *llvm::createAMDGPUDelimitInstGroupsPass(TargetMachine &tm) {
 bool AMDGPUDelimitInstGroupsPass::runOnMachineFunction(MachineFunction &MF)
 {
 //  MF.dump();
-  const AMDGPURegisterInfo * TRI =
-                  static_cast<const AMDGPURegisterInfo*>(TM.getRegisterInfo());
+  const R600RegisterInfo * TRI =
+                  static_cast<const R600RegisterInfo*>(TM.getRegisterInfo());
   for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
                                                   BB != BB_E; ++BB) {
     MachineBasicBlock &MBB = *BB;
@@ -124,7 +125,7 @@ bool AMDGPUDelimitInstGroupsPass::runOnMachineFunction(MachineFunction &MF)
       if (MI.getOpcode() == AMDIL::SET_CHAN) {
         element = MI.getOperand(2).getImm();
       } else {
-        element = getRegElement(TRI, dstReg);
+        element = TRI->getHWRegChan(dstReg);
       }
       if (currentLast > -1 && element <= (unsigned)currentLast) {
         endGroup(MBB, MF, lastRealInst);
@@ -187,7 +188,7 @@ void AMDGPUDelimitInstGroupsPass::addConstantReads(MachineInstr &MI)
     if (!MO.isReg()) {
       continue;
     }
-    if (AMDIL::R600_CReg_32RegClass.contains(MO.getReg())) {
+    if (AMDIL::R600_CReg32RegClass.contains(MO.getReg())) {
       constantReads[MO.getReg()] = true;
     }
   }
diff --git a/src/gallium/drivers/radeon/AMDGPUFixRegClasses.cpp b/src/gallium/drivers/radeon/AMDGPUFixRegClasses.cpp
index f3be5eb4776..27bcaac72d0 100644
--- a/src/gallium/drivers/radeon/AMDGPUFixRegClasses.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUFixRegClasses.cpp
@@ -76,7 +76,7 @@ bool AMDGPUFixRegClassesPass::runOnMachineFunction(MachineFunction &MF)
 
         const TargetRegisterClass * TRC = MRI.getRegClass(MO.getReg());
         if (TRC->getID() == AMDIL::GPRV4F32RegClassID) {
-          MRI.setRegClass(MO.getReg(), &AMDIL::REPLRegClass);
+          MRI.setRegClass(MO.getReg(), &AMDIL::R600_Reg128RegClass);
         }
       }
     }
diff --git a/src/gallium/drivers/radeon/AMDGPUGenShaderPatterns.pl b/src/gallium/drivers/radeon/AMDGPUGenShaderPatterns.pl
index 448883e8fa9..77ca11a6fa3 100644
--- a/src/gallium/drivers/radeon/AMDGPUGenShaderPatterns.pl
+++ b/src/gallium/drivers/radeon/AMDGPUGenShaderPatterns.pl
@@ -30,11 +30,13 @@ use AMDGPUConstants;
 
 my $reg_prefix = $ARGV[0];
 
-for (my $i = 0; $i < CONST_REG_COUNT; $i++) {
+for (my $i = 0; $i < CONST_REG_COUNT * 4; $i++) {
+  my $index = get_hw_index($i);
+  my $chan = get_chan_str($i);
 print <<STRING;
 def : Pat <
   (int_AMDGPU_load_const $i),
-  (f32 (MOV (f32 $reg_prefix$i)))
+  (f32 (MOV (f32 $reg_prefix$index\_$chan)))
 >;
 STRING
 }
diff --git a/src/gallium/drivers/radeon/AMDGPURegisterInfo.h b/src/gallium/drivers/radeon/AMDGPURegisterInfo.h
index 37c7f1ec619..b6a65f1a414 100644
--- a/src/gallium/drivers/radeon/AMDGPURegisterInfo.h
+++ b/src/gallium/drivers/radeon/AMDGPURegisterInfo.h
@@ -44,14 +44,6 @@ namespace llvm {
 
     virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
 
-    /* This is used to help calculate the index of a register.  A return value
-     * of true means that the index of any register in this class may be
-     * calcluated in this way:
-     * TargetRegisterClass * TRC;
-     * index = register - TRC->getRegister(0);
-     */
-    virtual bool isBaseRegClass(unsigned regClassID) const = 0;
-
     virtual const TargetRegisterClass *
     getISARegClass(const TargetRegisterClass * rc) const = 0;
   };
diff --git a/src/gallium/drivers/radeon/AMDGPUUtil.cpp b/src/gallium/drivers/radeon/AMDGPUUtil.cpp
index 1374444aae7..1975501d1c9 100644
--- a/src/gallium/drivers/radeon/AMDGPUUtil.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUUtil.cpp
@@ -50,33 +50,6 @@ bool llvm::isPlaceHolderOpcode(unsigned opcode)
   }
 }
 
-/* For f32 registers, this returns the corresponding element (X,Y,Z, or W) of
- * the v4f32 super register that it belongs to.
- */
-unsigned llvm::getRegElement(const AMDGPURegisterInfo * TRI, unsigned regNo)
-{
-  if (AMDIL::REPLRegisterClass->contains(regNo)
-      || AMDIL::SPECIALRegisterClass->contains(regNo)
-      || regNo == AMDIL::ALU_LITERAL_X) {
-    return 0;
-  } else {
-    return getHWRegNum(TRI, regNo) % 4;
-  }
-}
-
-unsigned llvm::getHWRegNum(const AMDGPURegisterInfo * TRI, unsigned amdilRegNo)
-{
-  for (TargetRegisterInfo::regclass_iterator RI = TRI->regclass_begin(),
-       RE = TRI->regclass_end(); RI != RE; ++RI) {
-    const TargetRegisterClass * TRC = *RI;
-    if (TRC->contains(amdilRegNo) && TRI->isBaseRegClass(TRC->getID())) {
-      return amdilRegNo - TRC->getRegister(0);
-    }
-  }
-  abort();
-  return 0;
-}
-
 bool llvm::isTransOp(unsigned opcode)
 {
   switch(opcode) {
diff --git a/src/gallium/drivers/radeon/AMDGPUUtil.h b/src/gallium/drivers/radeon/AMDGPUUtil.h
index 956d1580d93..4ec95a423ca 100644
--- a/src/gallium/drivers/radeon/AMDGPUUtil.h
+++ b/src/gallium/drivers/radeon/AMDGPUUtil.h
@@ -40,9 +40,6 @@ class TargetRegisterInfo;
 
 bool isPlaceHolderOpcode(unsigned opcode);
 
-unsigned getRegElement(const AMDGPURegisterInfo * TRI, unsigned regNo);
-unsigned getHWRegNum(const AMDGPURegisterInfo * TRI, unsigned amdilRegNo);
-
 bool isTransOp(unsigned opcode);
 bool isTexOp(unsigned opcode);
 bool isReductionOp(unsigned opcode);
diff --git a/src/gallium/drivers/radeon/R600CodeEmitter.cpp b/src/gallium/drivers/radeon/R600CodeEmitter.cpp
index cfca4b743a8..f04c5d17ce9 100644
--- a/src/gallium/drivers/radeon/R600CodeEmitter.cpp
+++ b/src/gallium/drivers/radeon/R600CodeEmitter.cpp
@@ -38,6 +38,8 @@
 #include "AMDGPU.h"
 #include "AMDGPUUtil.h"
 
+#include "R600RegisterInfo.h"
+
 #include <stdio.h>
 
 #define SRC_BYTE_COUNT 11
@@ -62,7 +64,7 @@ namespace {
   const TargetMachine * TM;
   const MachineRegisterInfo * MRI;
   AMDILMachineFunctionInfo * MFI;
-  const AMDGPURegisterInfo * TRI;
+  const R600RegisterInfo * TRI;
   bool evergreenEncoding;
 
   bool isReduction;
@@ -103,7 +105,6 @@ namespace {
   unsigned getHWReg(unsigned regNo);
 
   unsigned getElement(unsigned regNo);
-  int getElement(MachineInstr &MI);
 
 };
 
@@ -163,7 +164,7 @@ bool R600CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
   TM = &MF.getTarget();
   MRI = &MF.getRegInfo();
   MFI = MF.getInfo<AMDILMachineFunctionInfo>();
-  TRI = static_cast<const AMDGPURegisterInfo *>(TM->getRegisterInfo());
+  TRI = static_cast<const R600RegisterInfo *>(TM->getRegisterInfo());
   const AMDILSubtarget &STM = TM->getSubtarget<AMDILSubtarget>();
   std::string gpu = STM.getDeviceName();
   if (!gpu.compare(0,3, "rv7")) {
@@ -209,6 +210,7 @@ bool R600CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
 void R600CodeEmitter::emitALUInstr(MachineInstr &MI)
 {
 
+  MI.dump();
   unsigned numOperands = MI.getNumOperands();
 
    /* Some instructions are just place holder instructions that represent
@@ -298,7 +300,7 @@ void R600CodeEmitter::emitSrc(const MachineOperand & MO)
     if (parent->getOpcode() == AMDIL::VEXTRACT_v4f32) {
       emitByte(parent->getOperand(2).getImm());
     } else {
-      emitByte(getRegElement(TRI, MO.getReg()));
+      emitByte(TRI->getHWRegChan(MO.getReg()));
     }
   } else {
     emitByte(0);
@@ -349,7 +351,7 @@ void R600CodeEmitter::emitDst(const MachineOperand & MO)
     } else if (parent->getOpcode() == AMDIL::VCREATE_v4f32) {
       emitByte(ELEMENT_X);
     } else {
-      emitByte(getRegElement(TRI, MO.getReg()));
+      emitByte(TRI->getHWRegChan(MO.getReg()));
     }
 
     /* Emit isClamped (1 byte) */
@@ -360,7 +362,7 @@ void R600CodeEmitter::emitDst(const MachineOperand & MO)
     }
 
     /* Emit writemask (1 byte).  */
-    if ((isReduction && reductionElement != getRegElement(TRI, MO.getReg()))
+    if ((isReduction && reductionElement != TRI->getHWRegChan(MO.getReg()))
          || MO.getTargetFlags() & MO_FLAG_MASK) {
       emitByte(0);
     } else {
@@ -614,42 +616,13 @@ unsigned R600CodeEmitter::getHWReg(unsigned regNo)
 {
   unsigned hwReg;
 
-  switch(regNo) {
-  case AMDIL::ZERO: return 248;
-  case AMDIL::ONE:
-  case AMDIL::NEG_ONE: return 249;
-  case AMDIL::HALF:
-  case AMDIL::NEG_HALF: return 252;
-  case AMDIL::ALU_LITERAL_X: return 253;
-  }
-
-  hwReg = getHWRegNum(TRI, regNo);
-  /* XXX: Clean this up */
-  if (AMDIL::REPLRegClass.contains(regNo)) {
-    return hwReg;
-  }
-  hwReg = hwReg / 4;
-  if (AMDIL::R600_CReg_32RegClass.contains(regNo)) {
+  hwReg = TRI->getHWRegIndex(regNo);
+  if (AMDIL::R600_CReg32RegClass.contains(regNo)) {
     hwReg += 512;
   }
   return hwReg;
 }
 
-int R600CodeEmitter::getElement(MachineInstr &MI)
-{
-  if (MI.getNumOperands() == 0 || !MI.getOperand(0).isReg()) {
-    return -1;
-  } else {
-    switch(MI.getOpcode()) {
-    case AMDIL::EXPORT_REG:
-    case AMDIL::SWIZZLE:
-      return -1;
-    default:
-      return getRegElement(TRI, MI.getOperand(0).getReg());
-    }
-  }
-}
-
 RegElement maskBitToElement(unsigned int maskBit)
 {
   switch (maskBit) {
diff --git a/src/gallium/drivers/radeon/R600GenRegisterInfo.pl b/src/gallium/drivers/radeon/R600GenRegisterInfo.pl
index 6c99492c21e..2fb8402d3b3 100644
--- a/src/gallium/drivers/radeon/R600GenRegisterInfo.pl
+++ b/src/gallium/drivers/radeon/R600GenRegisterInfo.pl
@@ -28,97 +28,161 @@ use warnings;
 
 use AMDGPUConstants;
 
-my $REPL_REG_COUNT = 100;
 my $CREG_MAX = CONST_REG_COUNT - 1;
+my $TREG_MAX = TEMP_REG_COUNT - 1;
 
 print <<STRING;
 
-class AMDGPUReg <bits<16> value, string name> : Register<name> {
-  field bits<16> Value;
-  let Value = value;
+class R600Reg <string name> : Register<name> {
   let Namespace = "AMDIL";
 }
 
-class AMDGPUInputReg <bits<16> value, string name, Register gprAlias> :
-    AMDGPUReg<value, name> {
+let Namespace = "AMDIL" in {
+  def sel_x : SubRegIndex;
+  def sel_y : SubRegIndex;
+  def sel_z : SubRegIndex;
+  def sel_w : SubRegIndex;
+}
 
-  let Aliases = [gprAlias];
+class R600Reg_128<string n, list<Register> subregs> : RegisterWithSubRegs<n, subregs> {
+  let Namespace = "AMDIL";
+  let SubRegIndices = [sel_x, sel_y, sel_z, sel_w];
 }
 
 STRING
 
 my $i;
 
-### CONSTANT REGS ###
+### REG DEFS ###
+
+my @creg_list = print_reg_defs(CONST_REG_COUNT * 4, "C");
+my @treg_list = print_reg_defs(TEMP_REG_COUNT * 4, "T");
 
-my @creg_list;
-for ($i = 0; $i < CONST_REG_COUNT; $i++) {
-  print const_reg($i);
-  $creg_list[$i] = "C$i";
+my @t128reg;
+for (my $i = 0; $i < TEMP_REG_COUNT; $i++) {
+  my $name = "T$i\_XYZW";
+  print qq{def $name : R600Reg_128 <"T$i.XYZW", [T$i\_X, T$i\_Y, T$i\_Z, T$i\_W] >;\n};
+  $t128reg[$i] = $name;
 }
 
-print 'def R600_CReg_32 : RegisterClass <"AMDIL", [f32, i32], 32, (sequence "C%u", 0, ', CONST_REG_COUNT - 1, ")>;\n";
+print <<STRING;
 
-sub const_reg {
-  my ($index) = @_;
-  return sprintf(qq{def C%d : AMDGPUReg <%d, "C%d">;\n}, $index, $index, $index);
+def ZERO : R600Reg<"0.0">;
+def HALF : R600Reg<"0.5">;
+def ONE : R600Reg<"1.0">;
+def NEG_HALF : R600Reg<"-0.5">;
+def NEG_ONE : R600Reg<"-1.0">;
+def PV_X : R600Reg<"pv.x">;
+def ALU_LITERAL_X : R600Reg<"literal.x">;
+
+def R600_CReg32 : RegisterClass <"AMDIL", [f32, i32], 32, (add
+    (sequence "C%u_X", 0, $CREG_MAX),
+    (sequence "C%u_Y", 0, $CREG_MAX),
+    (sequence "C%u_Z", 0, $CREG_MAX),
+    (sequence "C%u_W", 0, $CREG_MAX))>;
+
+def R600_TReg32 : RegisterClass <"AMDIL", [f32, i32], 32, (add
+    (sequence "T%u_X", 0, $TREG_MAX),
+    (sequence "T%u_Y", 0, $TREG_MAX),
+    (sequence "T%u_Z", 0, $TREG_MAX),
+    (sequence "T%u_W", 0, $TREG_MAX))>;
+    
+def R600_Reg32 : RegisterClass <"AMDIL", [f32, i32], 32, (add
+    (sequence "C%u_X", 0, $CREG_MAX),
+    (sequence "C%u_Y", 0, $CREG_MAX),
+    (sequence "C%u_Z", 0, $CREG_MAX),
+    (sequence "C%u_W", 0, $CREG_MAX),
+    (sequence "T%u_X", 0, $TREG_MAX),
+    (sequence "T%u_Y", 0, $TREG_MAX),
+    (sequence "T%u_Z", 0, $TREG_MAX),
+    (sequence "T%u_W", 0, $TREG_MAX),
+    ZERO, HALF, ONE, PV_X, ALU_LITERAL_X, NEG_ONE, NEG_HALF)>;
+
+def R600_Reg128 : RegisterClass<"AMDIL", [v4f32], 128,
+    (sequence "T%u_XYZW", 0, $TREG_MAX)>
+{
+  let SubRegClasses = [(R600_TReg32 sel_x, sel_y, sel_z, sel_w)];
 }
 
-print <<STRING;
+STRING
 
-def ZERO : AMDILReg<871, "0.0">;
-def HALF : AMDILReg<872, "0.5">;
-def ONE : AMDILReg<873, "1.0">;
-def NEG_HALF : AMDILReg<874, "-0.5">;
-def NEG_ONE : AMDILReg<875, "-1.0">;
-def PV_X : AMDILReg<876, "pv.x">;
-def ALU_LITERAL_X : AMDILReg<877, "literal.x">;
+my %index_map;
+my %chan_map;
 
-def R600_Reg32 : RegisterClass <"AMDIL", [f32, i32], 32, (add
-  (sequence "C%u", 0, $CREG_MAX),
-  (sequence "R%u", 1, 128), ZERO, HALF, ONE, PV_X, ALU_LITERAL_X)>;
+for ($i = 0; $i <= $#creg_list; $i++) {
+  push(@{$index_map{get_hw_index($i)}}, $creg_list[$i]);
+  push(@{$chan_map{get_chan_str($i)}}, $creg_list[$i]);
+}
 
-let Namespace = "AMDIL" in {
-def sel_x : SubRegIndex;
-def sel_y : SubRegIndex;
-def sel_z : SubRegIndex;
-def sel_w : SubRegIndex;
+for ($i = 0; $i <= $#treg_list; $i++) {
+  push(@{$index_map{get_hw_index($i)}}, $treg_list[$i]);
+  push(@{$chan_map{get_chan_str($i)}}, $treg_list[$i]);
 }
 
-class AMDGPURegWithSubReg<string n, list<Register> subregs> : RegisterWithSubRegs<n, subregs> {
-  let Namespace = "AMDIL";
-  let SubRegIndices = [sel_x, sel_y, sel_z, sel_w];
+for ($i = 0; $i <= $#t128reg; $i++) {
+  push(@{$index_map{$i}}, $t128reg[$i]);
+  push(@{$chan_map{'X'}}, $t128reg[$i]);
 }
 
-STRING
+open(OUTFILE, ">", "R600HwRegInfo.inc");
 
-### REPL REGS ###
-my @repl_reg_list;
+print OUTFILE <<STRING;
 
-for (my $i = 0; $i < $REPL_REG_COUNT; $i++) {
-  print repl_reg($i);
-  $repl_reg_list[$i] = "REPL$i";
+unsigned R600RegisterInfo::getHWRegIndexGen(unsigned reg) const
+{
+  switch(reg) {
+  default: assert(!"Unknown register"); return 0;
+STRING
+foreach my $key (keys(%index_map)) {
+  foreach my $reg (@{$index_map{$key}}) {
+    print OUTFILE "  case AMDIL::$reg:\n";
+  }
+  print OUTFILE "    return $key;\n\n";
 }
 
-print 'def REPL : RegisterClass<"AMDIL", [v4f32], 128, (sequence "REPL%u", 0, ', $REPL_REG_COUNT - 1, ')';
-print ">;\n\n";
+print OUTFILE "  }\n}\n\n";
 
-sub repl_reg {
-  my ($index) = @_;
+print OUTFILE <<STRING;
 
-  return sprintf(qq{def REPL%d : AMDGPURegWithSubReg<"R%d.xyzw", [R%d, R%d, R%d, R%d]>;\n},
-    $index, $index, ($index * 4) + 1, ($index * 4) + 2, ($index * 4) + 3, ($index * 4) + 4);
-}
+unsigned R600RegisterInfo::getHWRegChanGen(unsigned reg) const
+{
+  switch(reg) {
+  default: assert(!"Unknown register"); return 0;
+STRING
 
-print <<STRING;
+foreach my $key (keys(%chan_map)) {
+  foreach my $reg (@{$chan_map{$key}}) {
+    print OUTFILE " case AMDIL::$reg:\n";
+  }
+  my $val;
+  if ($key eq 'X') {
+    $val = 0;
+  } elsif ($key eq 'Y') {
+    $val = 1;
+  } elsif ($key eq 'Z') {
+    $val = 2;
+  } elsif ($key eq 'W') {
+    $val = 3;
+  } else {
+    die("Unknown chan value; $key");
+  }
+  print OUTFILE "    return $val;\n\n";
+}
 
-def ADDR0 : AMDILReg<870, "addr0">;
+print OUTFILE "  }\n}\n\n";
 
-def RELADDR : RegisterClass<"AMDIL", [i32], 32,
-  (add ADDR0)
->;
+sub print_reg_defs {
+  my ($count, $prefix) = @_;
 
+  my @reg_list;
 
-def SPECIAL : RegisterClass<"AMDIL", [f32], 32, (add ZERO, HALF, ONE, NEG_HALF, NEG_ONE, PV_X)>; 
+  for ($i = 0; $i < $count; $i++) {
+    my $hw_index = get_hw_index($i);
+    my $chan= get_chan_str($i);
+    my $name = "$prefix$hw_index\_$chan";
+    print qq{def $name : R600Reg <"$prefix$hw_index.$chan">;\n};
+    $reg_list[$i] = $name;
+  }
+  return @reg_list;
+}
 
-STRING
diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td
index 83c64b896c0..66f8ebd7616 100644
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -104,8 +104,8 @@ class R600_REDUCTION <bits<32> inst, dag ins, string asm, list<dag> pattern,
 class R600_TEX <bits<32> inst, string opName, list<dag> pattern,
                 InstrItinClass itin = AnyALU> :
   InstR600 <inst,
-          (outs REPL:$dst),
-          (ins REPL:$src0, i32imm:$src1, i32imm:$src2),
+          (outs R600_Reg128:$dst),
+          (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2),
           !strconcat(opName, "$dst, $src0, $src1, $src2"),
           pattern,
           itin
@@ -229,42 +229,42 @@ def AND_INT : R600_2OP <
 
 def TEX_SAMPLE : R600_TEX <
   0x10, "TEX_SAMPLE",
-  [(set REPL:$dst, (int_AMDGPU_tex REPL:$src0, imm:$src1, imm:$src2))]
+  [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, imm:$src2))]
 >;
 
 def TEX_SAMPLE_C : R600_TEX <
   0x18, "TEX_SAMPLE_C",
-  [(set REPL:$dst, (int_AMDGPU_tex REPL:$src0, imm:$src1, TEX_SHADOW:$src2))]
+  [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
 >;
 
 def TEX_SAMPLE_L : R600_TEX <
   0x11, "TEX_SAMPLE_L",
-  [(set REPL:$dst, (int_AMDGPU_txl REPL:$src0, imm:$src1, imm:$src2))]
+  [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, imm:$src2))]
 >;
 
 def TEX_SAMPLE_C_L : R600_TEX <
   0x19, "TEX_SAMPLE_C_L",
-  [(set REPL:$dst, (int_AMDGPU_txl REPL:$src0, imm:$src1, TEX_SHADOW:$src2))]
+  [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
 >;
 
 def TEX_SAMPLE_LB : R600_TEX <
   0x12, "TEX_SAMPLE_LB",
-  [(set REPL:$dst, (int_AMDGPU_txb REPL:$src0, imm:$src1, imm:$src2))]
+  [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, imm:$src2))]
 >;
 
 def TEX_SAMPLE_C_LB : R600_TEX <
   0x1A, "TEX_SAMPLE_C_LB",
-  [(set REPL:$dst, (int_AMDGPU_txb REPL:$src0, imm:$src1, TEX_SHADOW:$src2))]
+  [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
 >;
 
 def TEX_SAMPLE_G : R600_TEX <
   0x14, "TEX_SAMPLE_G",
-  [(set REPL:$dst, (int_AMDGPU_txd REPL:$src0, imm:$src1, imm:$src2))]
+  [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, imm:$src1, imm:$src2))]
 >;
 
 def TEX_SAMPLE_C_G : R600_TEX <
   0x1C, "TEX_SAMPLE_C_G",
-  [(set REPL:$dst, (int_AMDGPU_txd REPL:$src0, imm:$src1, TEX_SHADOW:$src2))]
+  [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
 >;
 
 } // End Gen R600_CAYMAN
@@ -305,9 +305,9 @@ class CNDGE_Common <bits<32> inst> : R600_3OP <
 
 class DOT4_Common <bits<32> inst> : R600_REDUCTION <
   inst,
-  (ins REPL:$src0, REPL:$src1),
+  (ins R600_Reg128:$src0, R600_Reg128:$src1),
   "DOT4 $dst $src0, $src1",
-  [(set R600_Reg32:$dst, (int_AMDGPU_dp4 REPL:$src0, REPL:$src1))]
+  [(set R600_Reg32:$dst, (int_AMDGPU_dp4 R600_Reg128:$src0, R600_Reg128:$src1))]
 >;
 
 class EXP_IEEE_Common <bits<32> inst> : R600_1OP <
@@ -493,21 +493,14 @@ let Gen = AMDGPUGen.EG_CAYMAN in {
 /* Other Instructions */
 
 let isCodeGenOnly = 1 in {
-
-  def ARL : AMDGPUShaderInst <
-    (outs RELADDR:$dst),
-    (ins R600_Reg32:$src),
-    "ARL $dst, $src",
-    [(set RELADDR:$dst, (int_AMDGPU_arl R600_Reg32:$src))]
-  >;
-
+/*
   def SWIZZLE : AMDGPUShaderInst <
     (outs GPRV4F32:$dst),
     (ins GPRV4F32:$src0, i32imm:$src1),
     "SWIZZLE $dst, $src0, $src1",
     [(set GPRV4F32:$dst, (int_AMDGPU_swizzle GPRV4F32:$src0, imm:$src1))]
   >;
-
+*/
 
   def LAST : AMDGPUShaderInst <
     (outs),
@@ -518,23 +511,23 @@ let isCodeGenOnly = 1 in {
 
   def GET_CHAN : AMDGPUShaderInst <
     (outs R600_Reg32:$dst),
-    (ins REPL:$src0, i32imm:$src1),
+    (ins R600_Reg128:$src0, i32imm:$src1),
     "GET_CHAN $dst, $src0, $src1",
     []
   >;
 
   def SET_CHAN : AMDGPUShaderInst <
-    (outs REPL:$dst),
+    (outs R600_Reg128:$dst),
     (ins R600_Reg32:$src0, i32imm:$src1),
     "SET_CHAN $dst, $src0, $src1",
     []
   >;
 
   def MULLIT : AMDGPUShaderInst <
-    (outs REPL:$dst),
+    (outs R600_Reg128:$dst),
     (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
     "MULLIT $dst, $src0, $src1",
-    [(set REPL:$dst, (int_AMDGPU_mullit R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))]
+    [(set R600_Reg128:$dst, (int_AMDGPU_mullit R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))]
   >;
 
 }
diff --git a/src/gallium/drivers/radeon/R600LowerShaderInstructions.cpp b/src/gallium/drivers/radeon/R600LowerShaderInstructions.cpp
index 3a374b9d3c5..983d8514ec8 100644
--- a/src/gallium/drivers/radeon/R600LowerShaderInstructions.cpp
+++ b/src/gallium/drivers/radeon/R600LowerShaderInstructions.cpp
@@ -51,7 +51,6 @@ namespace {
     void lowerLOAD_INPUT(MachineInstr & MI);
     bool lowerSTORE_OUTPUT(MachineInstr & MI, MachineBasicBlock &MBB,
         MachineBasicBlock::iterator I);
-    void lowerSWIZZLE(MachineInstr &MI);
 
   public:
     R600LowerShaderInstructionsPass(TargetMachine &tm) :
@@ -114,10 +113,6 @@ bool R600LowerShaderInstructionsPass::runOnMachineFunction(MachineFunction &MF)
         deleteInstr = lowerSTORE_OUTPUT(MI, MBB, I);
         break;
 
-      case AMDIL::SWIZZLE:
-        lowerSWIZZLE(MI);
-        deleteInstr = true;
-        break;
       }
 
       ++I;
@@ -145,7 +140,7 @@ void R600LowerShaderInstructionsPass::lowerLOAD_INPUT(MachineInstr &MI)
   MachineOperand &dst = MI.getOperand(0);
   MachineOperand &arg = MI.getOperand(1);
   int64_t inputIndex = arg.getImm();
-  const TargetRegisterClass * inputClass = TM.getRegisterInfo()->getRegClass(AMDIL::GPRF32RegClassID);
+  const TargetRegisterClass * inputClass = TM.getRegisterInfo()->getRegClass(AMDIL::R600_TReg32RegClassID);
   unsigned newRegister = inputClass->getRegister(inputIndex);
   unsigned dstReg = dst.getReg();
 
@@ -159,7 +154,7 @@ bool R600LowerShaderInstructionsPass::lowerSTORE_OUTPUT(MachineInstr &MI,
   MachineOperand &indexOp = MI.getOperand(2);
   unsigned valueReg = valueOp.getReg();
   int64_t outputIndex = indexOp.getImm();
-  const TargetRegisterClass * outputClass = TM.getRegisterInfo()->getRegClass(AMDIL::GPRF32RegClassID);
+  const TargetRegisterClass * outputClass = TM.getRegisterInfo()->getRegClass(AMDIL::R600_TReg32RegClassID);
   unsigned newRegister = outputClass->getRegister(outputIndex);
 
   BuildMI(MBB, I, MBB.findDebugLoc(I), TM.getInstrInfo()->get(AMDIL::COPY),
@@ -172,20 +167,3 @@ bool R600LowerShaderInstructionsPass::lowerSTORE_OUTPUT(MachineInstr &MI,
   return true;
 
 }
-
-void R600LowerShaderInstructionsPass::lowerSWIZZLE(MachineInstr &MI)
-{
-  MachineOperand &dstOp = MI.getOperand(0);
-  MachineOperand &valOp = MI.getOperand(1);
-  MachineOperand &swzOp = MI.getOperand(2);
-  int64_t swizzle = swzOp.getImm();
-
-  /* Set the swizzle for all of the uses */
-  for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(dstOp.getReg()),
-       UE = MRI->use_end(); UI != UE; ++UI) {
-    UI.getOperand().setTargetFlags(swizzle);
-  }
-
-  /* Progate the swizzle instruction */
-  MRI->replaceRegWith(dstOp.getReg(), valOp.getReg());
-}
diff --git a/src/gallium/drivers/radeon/R600RegisterInfo.cpp b/src/gallium/drivers/radeon/R600RegisterInfo.cpp
index aea7595f52a..71d8b0b78c2 100644
--- a/src/gallium/drivers/radeon/R600RegisterInfo.cpp
+++ b/src/gallium/drivers/radeon/R600RegisterInfo.cpp
@@ -48,8 +48,10 @@ BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const
   Reserved.set(AMDIL::NEG_ONE);
   Reserved.set(AMDIL::PV_X);
   Reserved.set(AMDIL::ALU_LITERAL_X);
-  for (unsigned i = AMDIL::C0; i <= AMDIL::C1023; i++) {
-    Reserved.set(i);
+
+  for (TargetRegisterClass::iterator I = AMDIL::R600_CReg32RegClass.begin(),
+                        E = AMDIL::R600_CReg32RegClass.end(); I != E; ++I) {
+    Reserved.set(*I);
   }
 
   for (MachineFunction::const_iterator BB = MF.begin(),
@@ -68,30 +70,45 @@ BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const
   return Reserved;
 }
 
-bool R600RegisterInfo::isBaseRegClass(unsigned regClassID) const
-{
-  switch(regClassID) {
-  case AMDIL::R600_CReg_32RegClassID:
-  case AMDIL::GPRF32RegClassID:
-  case AMDIL::REPLRegClassID:
-    return true;
-  default:
-    return false;
-  }
-}
-
 const TargetRegisterClass *
 R600RegisterInfo::getISARegClass(const TargetRegisterClass * rc) const
 {
   switch (rc->getID()) {
   case AMDIL::GPRV4F32RegClassID:
   case AMDIL::GPRV4I32RegClassID:
-    return &AMDIL::REPLRegClass;
+    return &AMDIL::R600_Reg128RegClass;
   case AMDIL::GPRF32RegClassID:
   case AMDIL::GPRI32RegClassID:
     return &AMDIL::R600_Reg32RegClass;
   default: return rc;
+  }
 }
 
+unsigned R600RegisterInfo::getHWRegIndex(unsigned reg) const
+{
+  switch(reg) {
+  case AMDIL::ZERO: return 248;
+  case AMDIL::ONE:
+  case AMDIL::NEG_ONE: return 249;
+  case AMDIL::HALF:
+  case AMDIL::NEG_HALF: return 252;
+  case AMDIL::ALU_LITERAL_X: return 253;
+  default: return getHWRegIndexGen(reg);
+  }
+}
 
+unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const
+{
+  switch(reg) {
+  case AMDIL::ZERO:
+  case AMDIL::ONE:
+  case AMDIL::NEG_ONE:
+  case AMDIL::HALF:
+  case AMDIL::NEG_HALF:
+  case AMDIL::ALU_LITERAL_X:
+    return 0;
+  default: return getHWRegChanGen(reg);
+  }
 }
+
+#include "R600HwRegInfo.inc"
diff --git a/src/gallium/drivers/radeon/R600RegisterInfo.h b/src/gallium/drivers/radeon/R600RegisterInfo.h
index 9d530c621a5..fb76281f560 100644
--- a/src/gallium/drivers/radeon/R600RegisterInfo.h
+++ b/src/gallium/drivers/radeon/R600RegisterInfo.h
@@ -45,10 +45,13 @@ namespace llvm {
 
     virtual BitVector getReservedRegs(const MachineFunction &MF) const;
 
-    virtual bool isBaseRegClass(unsigned regClassID) const;
-
     virtual const TargetRegisterClass *
     getISARegClass(const TargetRegisterClass * rc) const;
+    unsigned getHWRegIndex(unsigned reg) const;
+    unsigned getHWRegChan(unsigned reg) const;
+private:
+    unsigned getHWRegChanGen(unsigned reg) const;
+    unsigned getHWRegIndexGen(unsigned reg) const;
   };
 } // End namespace llvm