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2013-04-03R600: Fix up test/CodeGen/R600/llvm.pow.ll for r177730HEADmesa-9.1.1masterMichel Danzer1-1/+1
2013-02-21R600: Fix for Unigine when MachineSched is enabledTom Stellard1-0/+28
2013-02-21R600/SI: Make sure M0 is loaded for V_INTERP_MOV_F32Michel Danzer1-0/+23
2013-02-19R600: Do not fold single instruction with more that 3 kcache readvljn1-0/+52
2013-02-13R600: Add support for 128-bit parameterststellar1-0/+18
2013-02-04R600: Add support for SET*_DX10 instructionsTom Stellard3-15/+150
2013-02-04R600: Add tests for unsupported condition codes.Tom Stellard1-0/+83
2013-02-01R600: Fix assembly name for SETGT_INTTom Stellard1-1/+1
2013-01-28R600: Add tests for instruction predicatesTom Stellard1-0/+100
2013-01-28R600: Emit function name in the AsmPrinterTom Stellard4-2/+15
2013-01-28R600: Fold clamp, neg, absVincent Lejeune1-2/+1
2013-01-04AMDGPU: Rename backend to R600Tom Stellard1-1/+1
2013-01-02DAGCombiner: Avoid generating illegal vector INT_TO_FP nodeststellar3-3/+37
2013-01-02Merge LLVM 3.2 branchTom Stellard83-322/+3724
2012-12-21R600: Expand vec4 INT <-> FP conversionststellar1-0/+52
2012-12-11R600: Add support for i8 and i16 function argumentsTom Stellard1-0/+37
2012-12-11R600: Improve assembly output for VTX instructionsTom Stellard2-2/+2
2012-12-05AMDGPU: add a pattern for min/maxTom Stellard2-8/+6
2012-12-05AMDGPU: replace int_AMDGPU_rcp by fdiv (1.0, x) in RECIP patternVincent Lejeune1-1/+1
2012-11-29R600: Fold immediates into ALU instructions when possible v2Tom Stellard6-5/+37
2012-11-13Merge master branchtstellar209-903/+7029
2012-10-22R600: Fix llvm.pow.ll testtstellar1-1/+1
2012-10-22Merge master branchtstellar51-76/+2050
2012-10-19R600: Use native operands for the MOV Instructiontstellar3-2/+3
2012-10-16Merge master branchtstellar83-406/+7829
2012-10-15R600: use floor intrinsic instead of llvm.AMDIL.floortstellar1-2/+2
2012-10-15R600: use llvm fabs intrinsictstellar1-2/+2
2012-10-15R600: add support for cos/sin intrinsictstellar2-6/+6
2012-10-11Merge master branchtstellar107-251/+2494
2012-10-09R600: Handle reversed true/false values in selectcctstellar1-0/+18
2012-10-09R600: Prefer lowering SELECT_CC to CND* instructions over SET* instructionststellar1-0/+16
2012-10-09R600: Fix lowering of fcmptstellar3-0/+43
2012-10-09R600: Add a pattern for: (selectcc i32, -1, i32, i32, SETGT)tstellar1-0/+21
2012-10-09R600: Add store v4i32 testtstellar1-0/+9
2012-10-09R600: Add tests for a few vector operationststellar7-0/+106
2012-10-03SI: Add sanity testtstellar1-0/+37
2012-10-02Merge master branchtstellar10-7/+233
2012-10-02R600: improve select_cc lowering to generate CND* more oftentstellar2-0/+22
2012-10-02Merge master branchtstellar74-99/+3549
2012-10-02Merge TOTtstellar11-6/+303
2012-09-24R600: Handle loads from the constants address space.tstellar1-0/+9
2012-09-24R600: Expand vector fadd and fmul on R600tstellar2-0/+30
2012-09-24R600: Add support for v4f32 stores on R600tstellar1-0/+9
2012-09-24R600: Add optimization for FP_ROUNDtstellar1-0/+11
2012-09-24R600: Add support for i8 reads on R600tstellar1-0/+10
2012-09-24R600: Replace AMDGPU pow intrinsic with the llvm versiontstellar1-2/+2
2012-09-24Address one of the original FIXMEs for the new SROA pass by implementingtstellar1-20/+43
2012-09-24Emit dtors into proper section while compiling in vcpp-compatible mode.tstellar1-6/+17
2012-09-24Switch to a signed representation for the dynamic offsets while walkingtstellar1-0/+58
2012-09-24Don't do actual work inside an assert statement. Fixes PR11760!tstellar3-0/+3
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