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2013-02-06R600: fix PHI value adding in the structurizerChristian König1-65/+81
2013-02-06R600/SI: cleanup VGPR encodingChristian König5-178/+16
2013-02-06R600/SI: Handle VGPR64 destination in copyPhysReg().Michel Dänzer1-1/+9
2013-02-06R600/SI: Add pattern for mul.Michel Dänzer1-0/+4
2013-02-06R600/SI: simplify and fix SMRD encodingChristian König6-154/+70
2013-02-06R600/SI: add proper 64bit immediate support v2Christian König3-12/+18
2013-02-06R600/SI: Add pattern for flog2.Michel Dänzer1-1/+3
2013-02-06R600: Fix 64-bit definesTom Stellard1-2/+2
2013-02-06R600: Add an explicit default processorTom Stellard1-0/+1
2013-02-04R600/SI: Use proper instructions for array/shadow samplers.Michel Dänzer2-4/+54
2013-02-04R600/SI: Make sample intrinsic address parameter type overloaded.Michel Dänzer3-22/+38
2013-02-04R600/SI: Add basic support for more integer vector types.Michel Dänzer5-11/+110
2013-02-04R600: Consolidate sub register indices.Michel Dänzer8-93/+73
2013-02-04R600: Add support for SET*_DX10 instructionsTom Stellard2-29/+131
2013-02-01R600: Fix assembly name for SETGT_INTTom Stellard1-1/+1
2013-01-29R600: Support for indirect addressing v3Tom Stellard30-74/+1124
2013-01-28R600: Fold remaining CONST_COPY after expand pseudo instVincent Lejeune2-12/+160
2013-01-28R600: improve inputs/interpolation handlingVadim Girlin10-252/+124
2013-01-28R600: Emit function name in the AsmPrinterTom Stellard1-0/+3
2013-01-28R600/SI: Add patterns for fcos and fsin.Michel Dänzer1-0/+10
2013-01-28R600: Fold clamp, neg, absVincent Lejeune1-3/+48
2013-01-28R600: Consider bitcast when folding const_address node.Vincent Lejeune2-0/+11
2013-01-28R600: Make store_dummy intrinsic more general by passing export typeVincent Lejeune2-4/+9
2013-01-18R600: add a llvm.R600.store.swizzle intrinsicsVincent Lejeune3-2/+31
2013-01-18R600: simplify stream outputs intrinsicVincent Lejeune5-47/+13
2013-01-18R600: rework handling of the constantsVadim Girlin16-104/+483
2013-01-18R600: Add a CONST_ADDRESS node to model constant buf readVincent Lejeune3-1/+12
2013-01-18R600: Factorise VTX_WORD0 and VTX_WORD1 in tblgen defVincent Lejeune1-45/+65
2013-01-16R600/SI: Use unnormalized coordinates for sampling with the RECT target.push-jan16Michel Dänzer2-0/+13
2013-01-16R600/SI: Take target parameter for sample intrinsics.Michel Dänzer2-4/+4
2013-01-16R600/SI: Derive all sample intrinsics from a single class.Michel Dänzer1-3/+5
2013-01-08R600: Proper insert S_WAITCNT instructionsChristian König7-32/+378
2013-01-08R600: Optimize and cleanup KILL on SIChristian König4-71/+96
2013-01-04AMDGPU: Rename backend to R600Tom Stellard106-37/+37
2013-01-02DAGCombiner: Avoid generating illegal vector INT_TO_FP nodeststellar1-4/+5
2013-01-02Merge LLVM 3.2 branchTom Stellard86-1404/+2050
2012-12-21R600: Coding style - remove empty spaces from the beginning of functionsTom Stellard3-35/+0
2012-12-21R600: Fix MAX_UINT definitionVadim Girlin1-1/+1
2012-12-21R600: Add SHADOWCUBE to TEX_SHADOW patternVadim Girlin1-1/+1
2012-12-21R600: Expand vec4 INT <-> FP conversionststellar1-0/+4
2012-12-14R600: Remove unecessary VREG alignment.Christian König1-6/+6
2012-12-14R600: control flow optimizationChristian König1-0/+49
2012-12-14R600: New control flow for SI v2Christian König13-384/+1498
2012-12-14R600: enable S_*N2_* instructionsChristian König1-4/+4
2012-12-14R600: BB operand support for SIChristian König4-4/+27
2012-12-14R600: remove nonsense setPrefLoopAlignmentChristian König1-1/+0
2012-12-11R600: Add an intrinsic to handle stream outputs.Vincent Lejeune6-0/+102
2012-12-11R600: Add a field for Export node (compMask) and factorise code handling stor...Vincent Lejeune2-42/+58
2012-12-11R600: Split Word0 and Word1 in Export instructionVincent Lejeune3-49/+60
2012-12-11AMDGPU/SI: Only allow selecting VGPRs with V_CNDMASK_B32.Michel Dänzer1-4/+4
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