diff options
| author | tstellar <tstellar@91177308-0d34-0410-b5e6-96231b3b80d8> | 2013-02-19 15:22:45 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-02-19 15:34:42 +0000 |
| commit | ff0f967c130937b8b6d166dc860537aea6af19d1 (patch) | |
| tree | 182405679f3ddab5cff58e4e99522d87bc35b07b | |
| parent | df25ff07367943d9d6945629eb5ef1efdb478466 (diff) | |
R600: Mark all members of the TRegMem register class as reserved
This stops the Machine Verifier from complaining about uses of undefined
physical registers.
NOTE: This is a candidate for the Mesa stable branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175518 91177308-0d34-0410-b5e6-96231b3b80d8
(cherry picked from commit f29f24339d64d5530a8ead396598ea76af717f50)
| -rw-r--r-- | lib/Target/R600/R600RegisterInfo.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/lib/Target/R600/R600RegisterInfo.cpp b/lib/Target/R600/R600RegisterInfo.cpp index 33e858dc046..bbd7995d7d5 100644 --- a/lib/Target/R600/R600RegisterInfo.cpp +++ b/lib/Target/R600/R600RegisterInfo.cpp @@ -49,6 +49,12 @@ BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const { Reserved.set(*I); } + for (TargetRegisterClass::iterator I = AMDGPU::TRegMemRegClass.begin(), + E = AMDGPU::TRegMemRegClass.end(); + I != E; ++I) { + Reserved.set(*I); + } + const R600InstrInfo *RII = static_cast<const R600InstrInfo*>(&TII); std::vector<unsigned> IndirectRegs = RII->getIndirectReservedRegs(MF); for (std::vector<unsigned>::iterator I = IndirectRegs.begin(), |