diff options
| author | Michel Danzer <michel.daenzer@amd.com> | 2013-02-21 08:57:10 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-02-21 15:20:22 +0000 |
| commit | ab73ecbfc912d2d5c37f7d3dbe7e7282fd6c9543 (patch) | |
| tree | 9e365a25d215f1d0bade8f7ae9d677e76a12609d | |
| parent | a58e8892a2225a5095cc9fc76f9f00d0b6ff50a8 (diff) | |
R600/SI: Make sure M0 is loaded for V_INTERP_MOV_F32
NOTE: This is a candidate for the Mesa stable branch.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175733 91177308-0d34-0410-b5e6-96231b3b80d8
(cherry picked from commit 74bf7a8467262ad60c8b13582bd6b07fd30b5550)
| -rw-r--r-- | lib/Target/R600/SIInstructions.td | 3 | ||||
| -rw-r--r-- | test/CodeGen/R600/llvm.SI.fs.interp.constant.ll | 23 |
2 files changed, 25 insertions, 1 deletions
diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td index 9372993dd44..2658aa09e02 100644 --- a/lib/Target/R600/SIInstructions.td +++ b/lib/Target/R600/SIInstructions.td @@ -1311,7 +1311,8 @@ def : Pat < def : Pat < (int_SI_fs_interp_constant imm:$attr_chan, imm:$attr, SReg_32:$params), - (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, SReg_32:$params) + (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, + (S_MOV_B32 SReg_32:$params)) >; def : Pat < diff --git a/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll b/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll new file mode 100644 index 00000000000..0c19f14cc45 --- /dev/null +++ b/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll @@ -0,0 +1,23 @@ +;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s + +;CHECK: S_MOV_B32 +;CHECK-NEXT: V_INTERP_MOV_F32 + +define void @main() { +main_body: + call void @llvm.AMDGPU.shader.type(i32 0) + %0 = load i32 addrspace(8)* inttoptr (i32 6 to i32 addrspace(8)*) + %1 = call float @llvm.SI.fs.interp.constant(i32 0, i32 0, i32 %0) + %2 = call i32 @llvm.SI.packf16(float %1, float %1) + %3 = bitcast i32 %2 to float + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %3, float %3, float %3, float %3) + ret void +} + +declare void @llvm.AMDGPU.shader.type(i32) + +declare float @llvm.SI.fs.interp.constant(i32, i32, i32) readonly + +declare i32 @llvm.SI.packf16(float, float) readnone + +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) |